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CY62158DV30
MoBL
8-Mbit (1024K x 8) MoBL
Static RAM
Features
• Very high speed: 45 ns, 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
• Ultra-low active power
— Typical active current:1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f
max
• Ultra-low standby power
• Easy memory expansion with CE
1
,
CE
2
, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and
44-pin TSOPII
This is ideal for providing More Battery Life™ (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 85% when
deselected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip
Enable 2 (CE
2
) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Functional Description
[1]
The CY62158DV30 is a high-performance CMOS static RAMs
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
CE
1
CE
2
WE
OE
Data in Drivers
I/O
0
I/O
1
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
1024K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines,
available at http://www.cypress.com.
A
13
A
14
A
15
A
16
A
17
A
18
A
19
Cypress Semiconductor Corporation
Document #: 38-05391 Rev. *D
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 17, 2004
CY62158DV30
MoBL
Pin Configuration
[2, 3, 4]
FBGA
Top View
1
DNU
2
OE
3
A
0
A
3
A
5
A
17
DNU
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
6
CE
2
A
B
C
D
E
F
G
H
DNU DNU
I/O
0
V
SS
V
CC
I/O
3
DNU
A
18
A
48TSOPI
A
Top View
DNU
I/O
1
I/O
2
DNU
NC
A
8
CE
1
DNU
DNU
I/O
5
I/O
6
DNU
WE
A
11
I/O
4
V
CC
V
SS
I/O
7
DNU
A
19
44 TSOPII
Top View
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE
2
DNU
DNU
DNU
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
A19
I/O7
DNU
I/O6
DNU
I/O5
DNU
I/O4
Vcc
DNU
I/O3
DNU
I/O2
DNU
I/O1
DNU
I/O0
OE
Vss
CE
1
A0
A
4
A
3
A
2
A
1
A
0
CE
1
DNU
DNU
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
DNU
DNU
WE
A
19
A
18
A
17
A
16
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
CE
2
A8
DNU
DNU
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
DNU
DNU
A
9
A
10
A
11
A
12
A
13
A
14
Notes:
2. NC pins are not internally connected to the die.
3. DNU pins have to be left floating.
4. The BYTE pin in the TSOPI package has to be tied LOW to use the device as 1M x 8 SRAM. The 48-TSOPI package can also be used as a 512K × 16 SRAM
by tying the BYTE signal HIGH. For 512K x 16 functionality, please refer to the CY62157DV30 data sheet.
Document #: 38-05391 Rev. *D
Page 2 of 11
CY62158DV30
MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Supply Voltage to Ground Potential .–0.3V to V
cc(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
......................... –0.3V to V
CC(max)
+ 0.3V
DC Input Voltage
[5, 6]
..................... –0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Product
CY62158DV30L
CY62158DV30LL
Range
Ambient
Temperature
(T
A
)
V
CC
[7]
Industrial –40°C to +85°C 2.2V – 3.6V
Product Portfolio
Power Dissipation
Operating I
CC
(mA)
V
CC
Range (V)
Product
CY62158DV30L
CY62158DV30LL
Min.
2.2
2.2
Typ.
[8]
3.0
3.0
Max.
3.6
3.6
Speed
(ns)
45,55,70
45,55,70
f = 1 MHz
Typ.
[8]
1.5
1.5
Max.
3
3
f = f
max
Typ.
[8]
12
12
Max.
20
15
Standby I
SB2
(µA)
Typ.
[8]
2
2
Max.
20
8
Electrical Characteristics
Over the Operating Range
CY62158DV30
Parameter
V
OH
V
OL
V
IH
V
IIL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
I
SB1
Automatic CE
Power-down Current —
CMOS Inputs
Automatic CE
Power-down Current —
CMOS Inputs
V
CC
= V
CCmax
L
I
OUT
= 0 mA LL
CMOS levels
L
LL
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V)
f = f
MAX
(Address and Data Only),
f = 0 (OE, and WE), V
CC
= 3.60V
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
L
LL
L
LL
2
2
2
2
Test Conditions
V
CC
= 2.20V
V
CC
= 2.70V
V
CC
= 2.20V
V
CC
= 2.70V
1.8
2.2
–0.3
–0.3
–1
–1
12
1.5
Min. Typ.
[8]
2.0
2.4
0.4
0.4
V
CC
+ 0.3V
V
CC
+ 0.3V
0.6
0.8
+1
+1
20
15
3
3
20
8
20
8
µA
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
I
SB2
Notes:
5. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+0.75V for pulse duration less than 20ns.
7. Full device AC operation assumes a 100
µs
ramp time from 0 to V
cc
(min) and 200
µs
wait time after V
cc
stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
Document #: 38-05391 Rev. *D
Page 3 of 11
CY62158DV30
MoBL
Capacitance
[9, 10.]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
10
10
Unit
pF
pF
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
Thermal
(Junction to Ambient)
Resistance
[9]
Test Conditions
Still Air, soldered on a 3 x 4.5 inch, four-layer
printed circuit board
BGA
72
8.86
TSOP II
75.13
8.95
TSOP I
74.88
8.6
Unit
°C/W
°C/W
Thermal Resistance
[9]
(Junction to Case)
AC Test Loads and Waveforms
[11]
R1
V
CC
OUTPUT
30 pF / 50 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
GND
10%
ALL INPUT PULSES
90%
90%
10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
TH
OUTPUT
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[9]
t
R[12]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
L
CE
1
> V
CC
−
0.2V or CE
2
<0.2V
LL
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
0
t
RC
Conditions
Min.
1.5
10
4
Typ.
[8]
Max.
Unit
V
µA
µA
ns
ns
Chip Deselect to Data
Retention Time
Operation Recovery
Time
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. The input capacitance on the CE
2
pin is 15 pF.
11. Test condition for the 45 ns part is a load capacitance of 30 pF.
12. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
>
100
µs.
Document #: 38-05391 Rev. *D
Page 4 of 11
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