PRELIMINARY
TECHNOLOGY, INC.
MT28F400
256K x 16, 512K x 8 FLASH MEMORY
FLASH MEMORY
FEATURES
• Seven erase blocks:
- 16KB/8K-word boot block (protected)
- Two 8KB/4K-word parameter blocks
- Four main memory blocks
• 5V
±10%
V
CC
; 12V
±5%
V
PP
• Address access times: 60ns, 80ns, 100ns
• Selectable organizations: 262,144 x 16 or
524,288 x 8
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Byte- or word-wide read and write
• TSOP packaging option
256K x 16, 512K x 8
5V/12V, BOOT BLOCK
PIN ASSIGNMENT (Top View)
44-Pin SOP
V
PP
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
Vss
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RST
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
OPTIONS
• Timing
60ns
80ns
100ns
• Boot-Block Starting Address
Top (3FFFFH)
Bottom (00000H)
MARKING
- 6
- 8
-10
T
B
SG
VG
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
56-Pin TSOP Type I
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RST
NC
NC
V
PP
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
A16
BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
Vss
CE
A0
NC
NC
• Packages
Plastic SOP (600 mil)
Plastic 56L TSOP Type 1 (14 x 20mm)
• Part Number Example: MT28F400SG-8 T
GENERAL DESCRIPTION
The MT28F400 is a nonvolatile, electrically block-
erasable (Flash), programmable read-only memory con-
taining 4,194,304 bits organized as 262,144 words by 16 bits
or 524,288 words by 8 bits. It is fabricated with Micron’s
advanced CMOS floating-gate process.
The MT28F400 is organized into seven separately erasable
blocks. To ensure that critical firmware is protected from
accidental erasure or overwrite, the MT28F400 features a
hardware-protected boot block. Writing or erasing the boot
block requires applying a super-voltage to the
?
R
/
ST pin in
/
addition to executing the normal write or erase sequences.
This block may be used to store code implemented in low-
level system recovery. The remaining blocks vary in density,
and are written-to and erased with no additional security
measures.
MT28F400
F01.pm5 – Rev. 6/95
The byte or word address is issued to read the memory
array with C
/
E and
?
O
/
E LOW and
?
W
/
E HIGH. Valid data is
?
output until the next address is issued. The
?
B
?
Y
?
T
/
E pin is
used to switch the data path between 8 bits wide and 16 bits
wide. When
?
B
?
YT
/
E is LOW, the dual-use pin DQ15/A-1
?
becomes the lowest order address bit (A-1). When
?
B
?
Y
?
T
/
E is
HIGH, the DQ15/A-1 pin becomes the most significant
data bit (DQ15).
1
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
MT28F400
F01.pm5 – Rev. 6/95
FUNCTIONAL BLOCK DIAGRAM
8
Input
Buffer
TECHNOLOGY, INC.
BYTE
I/O
Control
7
16KB Boot block
18
9
96KB Main block
Input
Buffer
A-1
Input Data
Latch/Mux
8KB Parameter block
8KB Parameter block
Input
Buffer
Logic
Addr.
Buffer/
A0 - A17
A9
9
128KB Main block
Latch
Addr.
Counter
128KB Main block
16
128KB Main block
Command
Execution
Logic
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Machine
Y-
Decoder
State
Power
(Current)
Control
X - Decoder / Block Erase Control
DQ15/A-1
DQ8 - DQ14
2
Vpp
Switch
Q15
Status
Register
Identification
Register
7
8
8
CE
OE
WE
7
DQ0 - DQ7
8
RST
V
PP
Output
Buffer
Output
Buffer
Output
Buffer
MUX
PRELIMINARY
MT28F400
256K x 16, 512K x 8 FLASH MEMORY
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT28F400
256K x 16, 512K x 8 FLASH MEMORY
PIN DESCRIPTIONS
SOP PIN
NUMBERS
43
TSOP PIN
NUMBERS
13
SYMBOL
?
W
/
E
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a write cycle. If W
/
E
?
is LOW, the cycle is either a write to the Command Execution
Logic (CEL) or to the memory array.
Chip Enable: Activates the device when LOW. When
/
C
/
E is
HIGH, the device is disabled and goes into standby power
mode.
Reset: Clears the status register, sets the Internal State
Machine (ISM) to the array read mode, and places the device in
standby mode when LOW. All inputs, including
/
C
/
E, are “don’t
care” and all outputs are High-Z. Also used to unlock boot block
when brought to V
HH
(boot-block unlock voltage; 12V). Must be
held HIGH during all other modes of operation.
Output Enable: Enables data output buffers when LOW. When
?
O
/
E is HIGH, the output buffers are disabled.
Byte Enable: If
/
B
/
Y
/
T
/
E = HIGH the upper byte is active through
DQ8-DQ15. If
/
B
/
Y
/
T
/
E = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/A-1 becomes the
least significant address input.
Address Inputs: Selects a unique, 16-bit word out of the
262,144 available. The DQ15/A-1 input becomes the lowest
order address when
/
B
/
Y
/
T
/
E = LOW to allow for selection of an
8-bit byte from 524,288 available.
Data I/O: MSB of data when
/
BY
/
T
/
E = HIGH. Address Input: LSB
/
of address input when
/
B
/
Y
/
T
/
E = LOW during read or write
operation.
Data I/O: Data output pins during any read operation, or data
input pins during a WRITE. Used to input commands to the CEL
for a command input.
Data I/O: Data output pins during any read operation or data
input pins during a WRITE when
/
B
/
Y
/
T
/
E = HIGH. High-Z when
/
B
/
Y
/
T
/
E is LOW.
No Connect: These pins may be driven or left unconnected.
12
32
?
C
/
E
Input
44
14
/
R
/
S
/
T
Input
14
33
34
54
?
O
/
E
/
B
/
Y
/
T
/
E
Input
Input
11, 10, 9, 8, 7,
6, 5, 4, 42, 41,
40, 39, 38, 37,
36, 35, 34, 3
31
31, 27, 26, 25,
24, 23, 22, 21,
10, 9, 8, 7, 6,
5, 4, 3, 55, 20
52
A0-A17
Input
DQ15/A-1
Input/
Output
Input/
Output
15, 17, 19, 21,
24, 26, 28, 30
16, 18, 20, 22,
25, 27, 29
2
35, 37, 39, 41, DQ0-DQ7
45, 47, 49, 51
36, 38, 40, 42, DQ8-DQ14 Input/
46, 48, 50
Output
1, 2, 11, 12,
15, 16, 18, 19,
28, 29, 30, 56
17
NC
-
1
V
PP
Supply
Write/Erase Supply Voltage: During a WRITE or ERASE
CONFIRM, V
PP
= V
PPH
(12V). V
PP
= “don’t care” during all other
operations.
Power Supply: +5V
±10%
Ground
23
13, 32
43, 44
33, 53
Vcc
Vss
Supply
Supply
MT28F400
F01.pm5 – Rev. 6/95
3
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT28F400
256K x 16, 512K x 8 FLASH MEMORY
TRUTH TABLE
1
FUNCTION
Standby
RESET
READING
16-bit Read
8-bit Read
Output Disable
ERASE SETUP
ERASE CONFIRM
3
WRITE SETUP
16-bit WRITE
4
8-bit WRITE
4
READ ARRAY
ERASE SETUP
ERASE CONFIRM
3
WRITE SETUP
16-bit WRITE
4
8-bit WRITE
4
READ ARRAY
Manufacturer (16-bit)
8
Manufacturer (8-bit)
Device (16-bit, top boot)
8
Device (8-bit, top boot)
Device (16-bit, bottom boot)
8
Device (8-bit, bottom boot)
NOTE:
H
H
H
H
H
H
H
H
H
H
V
HH
H
V
HH
V
HH
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
H
L
X
H
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
X
X
X
X
V
PPH
X
V
PPH
V
PPH
X
X
V
PPH
X
V
PPH
V
PPH
X
X
X
X
X
X
X
Data-Out
Data-Out
High-Z
20H
D0H
10H/40H
Data-In
Data-In
FFH
20H
D0H
10H/40H
Data-In
Data-In
FFH
2CH
2CH
B0H
B0H
B1H
B1H
Data-Out
High-Z
High-Z
X
X
X
Data-In
High-Z
X
X
X
X
Data-In
High-Z
X
00H
High-Z
44H
High-Z
44H
High-Z
Data-Out
A-1
High-Z
X
X
X
Data-In
A-1
X
X
X
X
Data-In
A-1
X
-
X
-
X
-
X
?
R
/
S
/
T
H
L
?
C
/
E
H
X
?
O
/
E
X
X
?
W
/
E
X
X
?
B
?
Y
/
T
/
E
X
X
A0
X
X
A9
X
X
V
PP
X
X
DQ0-DQ7
High-Z
High-Z
DQ8-DQ14
High-Z
High-Z
DQ15/A-1
High-Z
High-Z
WRITE/ERASE (EXCEPT BOOT BLOCK)
2
WRITE/ERASE (BOOT BLOCK)
2, 5
DEVICE IDENTIFICATION
6, 7
1. L = V
IL
, H = V
IH
, X = V
IL
or V
IH
.
2. V
PPH
= 12V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. V
HH
= 12V.
6. V
ID
= 12V; may also be read by issuing the IDENTIFY DEVICE Command.
7. A1-A8, A10-A17 = V
IL
.
8. Value reflects DQ8-DQ15.
MT28F400
F01.pm5 – Rev. 6/95
4
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT28F400
256K x 16, 512K x 8 FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F400 Flash memory incorporates a number of
features to make it ideally suited for system firmware.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting data
stored in other blocks. These memory blocks are read,
written and erased by issuing commands to the Command
Execution Logic (CEL). The CEL controls the operation of
the Internal State Machine (ISM), which completely con-
trols all write, block erase, and verify operations. The ISM
protects each memory location from over-erasure and
optimizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for writing the device in-system or in an external
programmer.
The Functional Description provides detailed informa-
tion on the operation of the MT28F400, and is organized into
these sections:
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (Read) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
Write/Erase Cycle Endurance
Power Usage
Powerup
during in-system firmware updates, should an uninten-
tional power fluctuation or system reset occur. The
MT28F400 is available in two versions; the MT28F400T
addresses the boot block starting from 3FFFFH, and the
MT28F400B addresses the boot block starting from 00000H.
CONFIGURABLE BUS SIZE
The MT28F400T/B allows dynamic selection of an 8-bit
(512K x 8) or 16-bit (256K x 16) data bus for reading and
writing the memory. The
?
B
/
Y
/
T
/
E pin is used to select the bus
width. When in the x16 configuration, control data is read
or written only on the lower 8 bits (DQ0-DQ7).
Data written to the memory array utilize all active data
pins for the selected configuration. When the x8 configura-
tion is selected, data is written in byte form; when in the x16
configuration, data is written in the word form.
INTERNAL STATE MACHINE (ISM)
Block erase and byte/word write timing are simplified
by using an ISM to control all erase and write algorithms in
the memory array. The ISM ensures protection against
over-erasure and optimizes write margin to each cell.
During write operations the ISM automatically incre-
ments and monitors write attempts, verifies write margin
on each memory cell, and updates the ISM status register.
When block erase is performed, the ISM automatically
overwrites the entire addressed block (eliminates over-
erasure), increments and monitors erase attempts, and sets
bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor to
monitor the status of the ISM during write and erase opera-
tions. Two bits of the 8-bit status register are set and cleared
entirely by the ISM. These bits indicate whether the ISM is
busy with an erase or write task and when an erase has been
suspended. Additional error information is set in three
other bits: valid V
PP
voltage, write error and erase error.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the device.
These commands control the operation of the ISM and the
read path (i.e. memory array, ID register, or status register).
Commands may be issued to the CEL while the ISM is
active. However, there are restrictions on what commands
are allowed in this condition. See the Command Execution
section for more detail.
OVERVIEW
SEVEN INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F400 is organized into seven independently
erasable memory blocks that allow portions of the memory
to be erased without affecting the rest of the memory data.
A special boot block is hardware-protected against inad-
vertent erasure or writes by a super-voltage pin. The volt-
age on this pin is required in addition to the 12V on the V
PP
pin. The remaining blocks require only the 12V V
PP
to be
present in order to be changed.
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or written
only when the R
/
S
/
T pin is taken to V
HH
. Designing a system
?
so that the processor or control logic is unable to apply 12V
to this pin will ensure data integrity in this memory block.
This provides additional security for the core firmware
MT28F400
F01.pm5 – Rev. 6/95
5
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
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