Operating Temperature Range (Note 2).... –40°C to 85°C
Specified Temperature Range (Note 3) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Junction Temperature ........................................... 150°C
24 23 22 21 20 19
GND 1
+IN 2
–IN 3
V
CM
4
V
CM
5
V
CC
6
UF PACKAGE
24-LEAD (4mm 4mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 37°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC6412CUF#PBF
LTC6412IUF#PBF
TAPE AND REEL
LTC6412CUF#TRPBF
LTC6412IUF#TRPBF
PART MARKING*
6412
6412
PACKAGE DESCRIPTION
24-Lead (4mm
×
4mm) Plastic QFN
24-Lead (4mm
×
4mm) Plastic QFN
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
6412f
2
LTC6412
DC ELECTRICAL CHARACTERISTICS
The
l
denotes specifications that apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. DC electrical performance measured using DC test circuit schematic.
V
IN(DIFF)
is defined as (+IN) – (–IN). V
OUT(DIFF)
is defined as (+OUT) – (–OUT). V
IN(CM)
is defined as [(+IN) + (–IN)]/2. V
OUT(CM)
is
defined as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are V
CC
= 3.3V,
EN
= 0.8V,
SHDN
= 2.2V, +V
G
tied
to V
REF
(negative gain slope mode), V
OUT(CM)
= 3.3V. Differential power gain defined at Z
SOURCE
= 50Ω differential and Z
LOAD
= 200Ω
differential.
SYMBOL
G
MAX
G
MIN
G
RANGE
TC
GAIN
G
SLOPE
G
CONF(AVE)
G
CONF(MAX)
PARAMETER
Maximum Differential Power Gain (Note 4)
Minimum Differential Power Gain (Note 4)
Differential Power Gain Range
Temperature Coefficient of Gain at Fixed V
G
Gain Control Slope
Average Conformance Error to Gain Slope Line
Maximum Conformance Error to Gain Slope
Line
Differential Input Resistance at Maximum Gain
Differential Input Resistance at Minimum Gain
CONDITIONS
–V
G
= 0V, V
IN(DIFF)
= 100mV
–V
G
= 1.2V, V
IN(DIFF)
= 200mV
G
MAX
-G
MIN
–V
G
= 0V to 1.2V
–V
G
= 0.2V to 1.0V, 85 Points, Slope of the
Least-Square Fit Line
–V
G
= 0.2V to 1.0V, 85 Points, Standard
Error to the Least-Square Fit Line
–V
G
= 0.2V to 1.0V, 85 points, Maximum
Error to the Least-Square Fit Line
–V
G
= 0V, V
IN(DIFF)
= 100mV
–V
G
= 1.2V, V
IN(DIFF)
= 200mV
49
47
49
47
l
MIN
16.1
15.5
–16.2
–16.8
30.7
30.1
–34.1
–34.7
TYP
17.1
–14.9
31.9
0.007
–32.9
0.12
0.20
MAX
18.1
18.7
–13.6
–13.0
33.1
33.7
–31.7
–31.1
0.20
0.45
UNITS
dB
dB
dB
dB
dB
dB
dB/°C
dB/V
dB/V
dB
dB
Gain Characteristics
l
l
l
+IN and –IN Pins
R
IN(GMAX)
R
IN(GMIN)
V
INCM(GMAX)
V
INCM(GMIN)
R
IH(+VG)
R
IH(–VG)
I
IL(+VG)
I
IL(–VG)
V
REF
57
57
640
640
7.8
7.2
7.8
7.2
–9
–10
–9
–10
590
580
9.2
9.2
–5
–5
615
10.6
11.6
10.6
11.6
–1
–1
–1
–1
640
650
l
l
65
67
65
67
Ω
Ω
Ω
Ω
mV
mV
kΩ
kΩ
kΩ
kΩ
μA
μA
μA
μA
mV
mV
Input Common Mode Voltage at Maximum Gain –V
G
= 0V, DC Blocking Capacitor to Input
Input Common Mode Voltage at Minimum Gain –V
G
= 1.2V, DC Blocking Capacitor to Input
+V
G
Input High Resistance
–V
G
Input High Resistance
+V
G
Input Low Current
–V
G
Input Low Current
Internal Bias Voltage
+V
G
= 1.0V, –V
G
Tied to V
REF
,
R
IN(+VG)
= 1V/Δ I
IL(+VG)
–V
G
= 1.0V, +V
G
Tied to V
REF
,
R
IN(–VG)
= 1V/Δ I
IL(–VG)
+V
G
= 0V, –V
G
Tied to V
REF
–V
G
= 0V, +V
G
Tied to V
REF
–V
G
= 0V, +V
G
Tied to V
REF
+V
G
, –V
G
, and V
REF
Pins
l
l
l
l
l
6412f
3
LTC6412
DC ELECTRICAL CHARACTERISTICS
The
l
denotes specifications that apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. DC electrical performance measured using DC test circuit schematic.
V
IN(DIFF)
is defined as (+IN) – (–IN). V
OUT(DIFF)
is defined as (+OUT) – (–OUT). V
IN(CM)
is defined as [(+IN) + (–IN)]/2. V
OUT(CM)
is
defined as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are V
CC
= 3.3V,
EN
= 0.8V,
SHDN
= 2.2V, +V
G
tied
to V
REF
(negative gain slope mode), V
OUT(CM)
= 3.3V. Differential power gain defined at Z
SOURCE
= 50Ω differential and Z
LOAD
= 200Ω
differential.
PARAMETER
SHDN
Input Low Voltage
SHDN
Input High Voltage
SHDN
Input Low Current
SHDN
Input High Current
EN
Input Low Voltage
EN
Input High Voltage
EN
Input Low Current
EN
Input High Current
Operating Supply Range
Total Supply Current
Sum of Supply Current to OUT Pins
Delta of Supply Current to OUT Pins
Supply Current in Shutdown
Power Supply Rejection Ratio at Max Gain
Power Supply Rejection Ratio at Min Gain
All V
CC
Pins Plus +OUT and –OUT Pins
I
S(OUT)
= I
+OUT
+ I
–OUT
Current Imbalance to +OUT and –OUT
l
SYMBOL
SHDN
Pin
V
IL(SHDN)
V
IH(SHDN)
I
IL(SHDN)
I
IH(SHDN)
EN
Pin
V
IL(EN)
V
IH(EN)
I
IL(EN)
I
IH(EN)
Power Supply
V
S
I
S(TOT)
I
S(OUT)
I
Δ(OUT)
I
S(SHDN)
PSRR
MAX
PSRR
MIN
CONDITIONS
l
l
MIN
TYP
MAX
0.8
UNITS
V
V
μA
μA
V
V
μA
μA
V
mA
mA
mA
mA
mA
mA
mA
mA
dB
dB
2.2
–60
–30
–30
–15
–1
–1
0.8
2.2
–60
–30
3.0
–30
–15
3.3
110
–1
–1
3.6
135
140
55
60
1.5
2.0
1.3
2.0
SHDN
= 0.8V
SHDN
= 2.2V
l
l
l
l
EN
= 0.8V
EN
= 2.2V
l
l
l
l
44
l
0.5
0.5
l
I
S(OUT)
at
SHDN
= 0.8V
–V
G
= 0V, Output Referred
–V
G
= 1.2V, Output Referred
40
40
53
53
6412f
4
LTC6412
AC ELECTRICAL CHARACTERISTICS
SYMBOL
Small Signal
BW
GMAX
BW
GMIN
Sdd11
Sdd22
Sdd12
–3dB Bandwidth for Sdd21 at Maximum Gain –V
G
= 0V, Test Circuit B
–3dB Bandwidth for Sdd21 at Minimum Gain
Input Match at Z
SOURCE
= 50Ω Differential
Output Match at Z
LOAD
= 200Ω Differential
Reverse Isolation
–V
G
= 1.2V, Test Circuit B
–V
G
= 0V to 1.2V, 10MHz-500MHz,
Test Circuit B
–V
G
= 0V to 1.2V, 10MHz-250MHz,
Test Circuit B
–V
G
= 0V to 1.2V, 10MHz-500MHz,
Test Circuit B
Peak P
OUT
= +4dBm, –V
G
= 0.2V to 0.4V,
Time to Settle Within 1dB of Final P
OUT
Peak P
OUT
= +4dBm, –V
G
= 0.2V to 0.6V,
Time to Settle Within 1dB of Final P
OUT
Peak P
OUT
= +4dBm, –V
G
= 0.2V to 0.8V,
Time to Settle Within 1dB of Final P
OUT
–V
G
= 0V, P
IN
= +3dBm to –17dBm, Time to
Settle Within 1dB of Final P
OUT
P
OUT
= 0dBm at
EN
= 0V, –V
G
= 0V,
EN
= 0V to 3V, Time for P
OUT
≤ –20dBm
P
OUT
= 0dBm at
EN
= 0V, –V
G
= 0V,
EN
= 3V to
0V, Time for P
OUT
≥ –1dBm
–V
G
= 0V, Test Circuit B
–V
G
= 1.2V, Test Circuit B
G
MAX
-G
MIN
P
OUT
= 0dBm, –V
G
= 0V to 1.0V
P
OUT
= 0dBm, –V
G
= 0V to 1.0V
f
1
= 69.5MHz, f
2
= 70.5MHz,
P
OUT
= –6dBm/Tone, –V
G
= 0V to 1.0V
f
1
= 69.5MHz, f
2
= 70.5MHz,
P
OUT
= –6dBm/Tone, –V
G
= 0V to 1.0V
–V
G
= 0V (Note 6)
–V
G
= 0V (Note 5)
–V
G
= 1.2V (Note 5)
–V
G
= 0V, Test Circuit B
–V
G
= 1.2V, Test Circuit B
G
MAX
-G
MIN
P
OUT
= 0dBm, –V
G
= 0V to 1.0V
P
OUT
= 0dBm, –V
G
= 0V to 1.0V
800
800
–20
–10
-80
MHz
MHz
dB
dB
dB
PARAMETER
The
l
denotes specifications that apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. Typical AC electrical performance measured in demo board DC1464A
(Figure 3, Test Circuit A) unless otherwise noted. Default operating conditions are V
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