HMMC-3002
DC – 16 GHz GaAs HBT MMIC Divide-by-2 Prescaler
Data Sheet
Chip Size:
Chip Size Tolerance:
Chip Thickness:
Pad Dimensions:
1330 x 440
µm
(52.4 x 17.3 mils)
±
10
µm
(± 0.4 mils)
127
±
15
µm
(5.0
±
0.6 mils)
70 x 70
µm
(2.8 x 2.8 mils)
Description
The HMMC-3002 GaAs HBT MMIC Prescaler offers
DC to 16 GHz frequency translation for use in
communications and EW systems incorporating
high-frequency PLL oscillator circuits and signal-
path down conversion applications. The prescaler
provides a large input power sensitivity window
and low phase noise. In addition to the features
listed above the device offers an input disable
contact pad to eliminate any self-oscillation condi-
tion.
Features
• Wide frequency range: 0.2 – 16 GHz
• High input power sensitivity:
On-chip pre- and post-amps
-20 to +10 dBm (1–10 GHz)
-15 to +10 dBm (10 – 12 GHz)
-10 to +5 dBm (12 – 15 GHz)
•
Dual mode P
out
: (chip form)
+6.0 dBm (0.99 V
p-p
) @ 80 mA
0 dBm (0.5 V
p-p
) @ 60 mA
•
•
•
•
Low phase noise: -153 dBc/Hz @ 100 kHz Offset
(+) or (-) single supply bias operation
Wide bias supply range: 4.5 to 6.5 volt operating range
Differental I/O with on-chip 50Ω matching
Absolute Maximum Ratings
[1]
(@ T
A
= 25°C, unless otherwise indicated)
Symbol
V
CC
V
EE
[V
CC
-V
EE
]
V
Disable
V
Logic
P
in (CW)
V
RFin
T
BS[2]
T
stg
T
max
Parameters/Conditions
Bias Supply Voltage
Bias Supply Voltage
Bias Supply Delta
Pre-amp Disable Voltage
Logic Threshold Voltage
CW RF Input Power
DC Input Voltage (@ RF
in
or RF
in
Ports)
Backside Operating Temperature
Storage Temperature
Max. Assembly Temp. (60 seconds max.)
Units
V
V
V
V
V
dBm
V
°C
°C
°C
Min.
Max.
+7
-7
+7
V
EE
V
CC
-1.5
V
CC
V
CC
-1.2
+10
V
CC
±
0.5
-40
-65
+85
+165
310
Notes:
1. Operation in excess of any parameter limit (except T
BS
) may result in permanent damage to this
device.
2. MTTF > 1 x10
6
hours @ T
BS
≤
85°C. Operation in excess of maximum operating temperature
(T
BS
) will degrade MTTF.
HMMC-3002 DC Specifications/Physical Properties
(@ T
A
= 25°C, V
CC
- V
EE
= 5.0 volts, unless otherwise indicated)
Symbol
V
CC
- V
EE
|I
CC
| or |I
EE
|
V
RFin(q)
V
RFout(q)
V
Logic
Parameters and Test Conditions
Operating bias supply difference
[1]
Bias supply current (High output power configuration
[2]
: V
PwrSel
= V
EE
)
Bias supply current (Low output power configuration: V
PwrSel
= open)
Quiescent DC voltage appearing at all RF ports
Nominal ECL Logic Level
(V
Logic
contact self-bias voltage, generated on-chip)
Units
V
mA
mA
V
V
Min.
4.5
68
51
Typ.
5.0
80
60
V
CC
Max.
6.5
92
69
V
CC
- 1.45
V
CC
- 1.35
V
CC
- 1.25
Notes:
1. Prescaler will operate over full specified supply voltage range. V
CC
or V
EE
not to exceed limits specified in Absolute Maximum Ratings section.
2. High output power configuration: P
out
= +6.0 dBm (V
out
= 0.99 V
p-p
), Low output power configuration: P
out
= 0 dBm (V
out
= 0.5 V
p-p
)
RF Specifications,
(T
A
= 25°C, Z
0
= 50Ω, V
CC
- V
EE
= 5.0 volts)
Symbol
ƒ
in(max)
ƒ
in(min)
ƒ
Self-Osc.
Parameters and Test Conditions
Maximum input frequency of operation
Minimum input frequency of operation
[1]
(P
in
= -10 dBm)
Output Self-Oscillation Frequency
[2]
@ DC, (Square-wave input)
@ ƒ
in
= 500 MHz, (Sine-wave input)
ƒ
in
= 1 to 10 GHz
ƒ
in
= 10 to 12 GHz
ƒ
in
= 12 to 15 GHz
Small-Signal Input/Output Return Loss
(@ƒ
in
<12 GHz)
Small-Signal Reverse Isolation
(@ƒ
in
<12 GHz)
SSB Phase Noise (@ P
in
= 0 dBm, 100 kHz offset
from a ƒ
out
= 1.2 GHz Carrier)
Input signal time variation @ zero-crossing
(ƒ
in
= 10 GHz, P
in
= -10 dBm)
Output transition time (10% to 90% rise/fall time)
Units
GHz
GHz
GHz
dBm
dBm
dBm
dBm
dBm
dB
dB
dBc/Hz
ps
ps
Min.
16
Typ.
18
0.2
6.8
Max.
0.5
P
in
-15
-15
-15
-10
-4
>-25
>-20
>-25
>-15
>-10
15
30
-153
1
70
+10
+10
+10
+10
+4
RL
S
12
ϕ
N
Jitter
Τ
r
or
Τ
f
Notes:
1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Pre-amp Disable
(V
Disable
) feature, or the Differental Input de-biasing technique.
2
Applications
The HMMC-3002 is designed for
use in high frequency communi-
cations, microwave instrumenta-
tion, and EW radar systems
where low phase-noise PLL
control circuitry or broad-band
frequency translation is required.
Operation
The device is designed to operate
when driven with either a single-
ended or differential sinusoidal
input signal over a 200 MHz to
16 GHz bandwidth. Below
200 MHz the prescaler input is
“slew-rate” limited, requiring fast
rising and falling edge speeds to
properly divide. The device will
operate at frequencies down to
DC when driven with a square-
wave. The device may be biased
from either a single positive or
single negative supply bias. The
back-side of the device is not DC
connected to any DC bias point
on the device. For positive supply
operation V
CC
is nominally
biased at any voltage in the +4.5
to +6.5 volt range with V
EE
(or
V
EE
& V
Pwr-Sel
) grounded. For
negative bias operation V
CC
is
typically grounded and a nega-
tive voltage between -4.5 to
-6.5 volts is applied to V
EE
(or
V
EE
& V
PwrSel
).
Several features are designed
into this prescaler:
1) Dual-Output Power Feature
Bonding both V
EE
and V
PwrSel
pads to either ground (positive
bias mode) or the negative
supply (negative bias mode), will
deliver ~0 dBm [0.5V
p-p
] at the
RF output port while drawing
~40 mA supply current. Elimi-
nating the V
PwrSel
connection
results in reduced output power
and voltage swing, -6.0 dBm
[0.25 V
p-p
] but at a reduced
current draw of ~30 mA result-
ing in less over-all power
dissipation. (NOTE: V
EE
must
ALWAYS be bonded and V
PwrSel
must NEVER be biased to any
potential other than V
EE
or
open-circuited.)
2) V
Logic
ECL Contact Pad
Under normal conditions no
connection or external bias is
required to this pad and it is self-
biased to the on-chip ECL logic
threshold voltage (V
CC
-1.35V).
The user can provide an external
bias to this pad (1.5 to 1.2 volts
less than V
CC
) to force the
prescaler to operate at a system
generated logic threshold voltage.
3) Input Disable Feature
If an RF signal with sufficient
signal to noise ratio is present at
the RF input, the prescaler will
operate and provide a divided
output equal to the input fre-
quency divided by the divide
modulus. Under certain “ideal”
conditions where the input is
well matched at the right input
frequency, the device may “self-
oscillate”, especially under small
signal input powers or with only
noise present at the input. This
“self-oscillation” will produce an
undesired output signal also
known as a false trigger. By
applying an external bias to the
input disable contact pad (more
positive than V
CC
- 1.35V), the
input preamplifier stage is locked
into either logic “high” or logic
“low” preventing frequency
division and any self-oscillation
frequency which may be present.
4) Input DC Offset
Another method used to prevent
false triggers or self-oscillation
conditions is to apply a 20 to
100 mV DC offset voltage be-
tween the RF
in
and RF
in
ports.
This prevents noise or spurious
low level signals from triggering
the divider.
Adding a 10KΩ resistor between
the unused RF input to a contact
point at the V
EE
potential will
result in an offset of
≈25mV
between the RF inputs. Note
however, that the input sensitiv-
ity will be reduced slightly due to
the presence of this offset.
Assembly Techniques
Figure 3 shows the chip assembly
diagram for single-ended I/O
operation through 12 GHz for
either positive or negative bias
supply operation. In either case
the supply contact to the chip
must be capacitively bypassed to
provide good input sensitivity
and low input power feedthrough.
Independent of the bias applied
to the device, the backside of the
chip should always be connected
to both a good RF ground plane
and a good thermal heat sinking
region on the mounting surface.
All RF ports are DC connected
on-chip to the V
CC
contact
through on-chip 50Ω resistors.
Under any bias conditions where
V
CC
is not DC grounded, the RF
ports should be AC coupled via
series capacitors mounted on the
thin-film substrate at each RF
port. Only under bias conditions
where V
CC
is DC grounded (as is
typical for negative bias supply
operation) may the RF ports be
direct coupled to adjacent cir-
cuitry or in some cases, such as
level shifting to subsequent
stages. In the latter case the
device backside may be “floated”
and bias applied as the difference
between V
CC
and V
EE
.
All bonds between the device and
this bypass capacitor should be
as short as possible to limit the
inductance. For operation at fre-
quencies below 1 GHz, a large
value capacitor must be added to
provide proper RF bypassing.
4
Due to on-chip 50Ω matching
resistors at all four RF ports, no
external termination is required
on any unused RF port. However,
improved “Spitback” perfor-
mance (~20 dB) and input sensi-
tivity can be achieved by termi-
nating the unused RFout port to
V
CC
through 50Ω (positive
supply) or to ground via a 50Ω
termination (negative supply
operation).
GaAs MMICs are ESD sensitive.
ESD preventive measures must
be employed in all aspects of
storage, handling, and assembly.
MMIC ESD precautions, handling
considerations, die attach and
bonding methods are critical fac-
tors in successful GaAs MMIC
performance and reliability.
Avago application note #54,
“GaAs MMIC ESD, Die Attach
and Bonding Guidelines” pro-
vides basic information on these
subjects.
Optional DC Operating Values/Logic Levels
(T
A
= 25°C)
Function
Symbol
Conditions
Min.
(volts/mA)
V
CC
- 1.5
V
Logic
+ 0.25
V
EE
V
D
> V
EE
+ 3
V
D
< V
EE
+ 3
Note:
1. Acceptable voltage range when applied from external source.
(V
Disable
- V
EE
- 3)/500
0
(V
Disable
- V
EE
- 3)/500
0
Typical
(volts/mA)
V
CC
- 1.35
V
Logic
Max.
(volts/mA)
V
CC
- 1.2
V
CC
V
Logic
- 0.25
(V
Disable
- V
EE
- 3)/500
0
Logic Threshold
[1]
V
Logic
V
Disable(High)
[Disable]
Input Disable
V
Disable(Low)
[Enable]
I
Disable
V
CC
V
CC
RFin
V
CC
RFin
RFout
V
CC
RFout
V
CCBypass
No Connection
V
Logic
V
Disable
V
EE
V
PwrSel
230
440
370
220
70
0
70
0
350
500
650
800
900
260
Notes:
• All dimensions in microns.
• All Pad Dim: 70 x 70
µm
(except where noted)
• Tolerances:
±10 µm
• Chip Thickness: 127
±
15
µm
950
1090
1260
1330
Figure 2. Pad Locations and Chip Dimensions.
5
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