74AUP1G373
Rev. 7 — 27 March 2020
Low-power D-type transparent latch; 3-state
Product data sheet
1. General description
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the
latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW,
the latch stores the information that was present at the D-input one set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at
the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation
of input pin OE does not affect the state of the latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times
across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire V
CC
range
from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
2. Features and benefits
•
•
•
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
•
JESD8-12 (0.8 V to 1.3 V)
•
JESD8-11 (0.9 V to 1.65 V)
•
JESD8-7 (1.2 V to 1.95 V)
•
JESD8-5 (1.8 V to 2.7 V)
•
JESD8-B (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F Class 3A exceeds 5000 V
•
MM JESD22-A115-A exceeds 200 V
•
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
•
•
•
•
•
•
Nexperia
74AUP1G373
Low-power D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74AUP1G373GW
74AUP1G373GM
74AUP1G373GF
74AUP1G373GN
74AUP1G373GS
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
SOT1115
SOT1202
4. Marking
Table 2. Marking
Type number
74AUP1G373GW
74AUP1G373GM
74AUP1G373GF
74AUP1G373GN
74AUP1G373GS
[1]
Marking code
[1]
aW
aW
aW
aW
aW
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
D
D
Q
Q
3
1
D
LE
OE
Q
4
1
3
6
C1
4
EN
001aae248
LE
LE
LE
OE
6
001aae247
001aae249
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram
74AUP1G373
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 27 March 2020
2 / 22
Nexperia
74AUP1G373
Low-power D-type transparent latch; 3-state
6. Pinning information
6.1. Pinning
74AUP1G373
74AUP1G373
LE
1
2
3
6
5
4
OE
V
CC
Q
74AUP1G373
LE
GND
D
1
2
3
001aae250
LE
1
6
OE
6
5
4
OE
V
CC
GND
2
5
V
CC
Q
GND
D
D
3
4
Q
001aae252
001aae251
Transparent top view
Transparent top view
Fig. 4.
Pin configuration SOT363
(SC-88)
Fig. 5.
Pin configuration SOT886
(XSON6)
Fig. 6.
Pin configuration SOT891,
SOT1115 and SOT1202
(XSON6)
6.2. Pin description
Table 3. Pin description
Symbol
LE
GND
D
Q
V
CC
OE
Pin
1
2
3
4
5
6
Description
latch enable input (active HIGH)
ground (0 V)
data input
latch output
supply voltage
output enable input (active LOW)
7. Functional description
Table 4. Function table
H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
X = Don’t care; Z = high-impedance OFF-state.
Operating modes
Input
OE
Enable and read register (transparent mode) L
L
Latch and read register
Latch register and disable outputs
L
L
H
LE
H
H
L
L
X
D
L
H
l
h
X
L
H
L
H
X
Internal latch Output
Q
L
H
L
H
Z
74AUP1G373
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 27 March 2020
3 / 22
Nexperia
74AUP1G373
Low-power D-type transparent latch; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< 0 V
[1]
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
[1]
Min
-0.5
-50
-0.5
-50
-0.5
-
-
-50
-65
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT363 (SC-88) package: P
tot
derates linearly with 3.7 mW/K above 83 °C.
For SOT886 (XSON6) package: P
tot
derates linearly with 3.3 mW/K above 74 °C.
For SOT891 (XSON6) package: P
tot
derates linearly with 3.3 mW/K above 74 °C.
For SOT1115 (XSON6) package: P
tot
derates linearly with 3.2 mW/K above 71 °C.
For SOT1202 (XSON6) package: P
tot
derates linearly with 3.3 mW/K above 74 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Min
0.8
0
0
0
-40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP1G373
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 27 March 2020
4 / 22
Nexperia
74AUP1G373
Low-power D-type transparent latch; 3-state
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25 °C
V
IH
HIGH-level input
voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input
voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 0.8 V to 3.6 V
I
O
= -1.1 mA; V
CC
= 1.1 V
I
O
= -1.7 mA; V
CC
= 1.4 V
I
O
= -1.9 mA; V
CC
= 1.65 V
I
O
= -2.3 mA; V
CC
= 2.3 V
I
O
= -3.1 mA; V
CC
= 2.3 V
I
O
= -2.7 mA; V
CC
= 3.0 V
I
O
= -4.0 mA; V
CC
= 3.0 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OZ
I
OFF
ΔI
OFF
input leakage current
OFF-state output
current
power-off leakage
current
additional power-off
leakage current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
= V
IH
or V
IL
; V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V to 0.2 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3 × V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
V
μA
μA
μA
μA
V
CC
- 0.1
0.75 × V
CC
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.70 × V
CC
0.65 × V
CC
1.6
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.30 × V
CC
0.35 × V
CC
0.7
0.9
V
V
V
V
V
V
V
V
Conditions
Min
Typ
Max
Unit
74AUP1G373
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 27 March 2020
5 / 22
Microchip MCU
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