PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM
Features
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Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
organized as 128K bytes of 8 bits each or 64K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
20 ns, 25 ns, and 45 ns Access Times
Internally Organized as 128K x 8 (CY14B101LA) or 64K x 16
(CY14B101NA)
Hands off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Infinite Read, Write, and Recall Cycles
200,000 STORE Cycles to QuantumTrap
20 year Data Retention
Single 3V +20% to -10% Operation
Commercial and Industrial Temperatures
54/44-Pin TSOP-II, 48-Pin SSOP, and 32-Pin SOIC Packages
Pb-free and RoHS Compliance
Logic Block Diagram
[1, 2, 3]
Notes
1. Address A
0
- A
16
for x8 configuration and Address A
0
- A
15
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-42879 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 09, 2009
[+] Feedb
PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts
Figure 1. Pin Diagram - 44 Pin TSOP II
NC
[7]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[6]
NC
NC
NC
[5]
A
16
[4]
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
[5]
A
15
OE
[4]
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
44 - TSOP II
(x8)
44 - TSOP II
(x16)
[8]
Top View
(not to scale)
Top View
(not to scale)
Figure 2. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
NC
A
4
NC
NC
NC
V
SS
NC
NC
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
WE
A
13
A
8
A
9
NC
A
11
NC
NC
NC
V
SS
NC
NC
DQ6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
48-SSOP
Top View
(not to scale)
Notes
4. Address expansion for 2 Mbit. NC pin not connected to die.
5. Address expansion for 4 Mbit. NC pin not connected to die.
6. Address expansion for 8 Mbit. NC pin not connected to die.
7. Address expansion for 16 Mbit. NC pin not connected to die.
8. HSB pin is not available in 44-TSOP II (x16) package.
Document #: 001-42879 Rev. *C
Page 2 of 24
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PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts
(continued)
Figure 3. Pin Diagram - 54-Pin TSOP II
NC
[7]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
NC
[6]
[5]
NC
[4]
NC
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
54 - TSOP II
(x16)
Top View
(
not to scale)
Table 1. Pin Definitions
Pin Name
A
0
– A
16
A
0
– A
15
DQ
0
– DQ
7
I/O Type
Input
Description
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration.
Used as input or output lines depending on operation.
DQ
0
– DQ
15
Input/Output
Bidirectional Data I/O Lines for x16 Configuration.
Used as input or output lines depending on
operation.
WE
CE
OE
BHE
BLE
V
SS
V
CC
HSB
[8]
Input
Input
Input
Input
Input
Ground
Power
Supply
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Byte High Enable, Active LOW.
Controls DQ
15
- DQ
8
.
Byte Low Enable, Active LOW.
Controls DQ
7
- DQ
0
.
Ground for the Device.
Must be connected to the ground of the system.
Power Supply Inputs to the Device.
3.0V +20%, –10%
Input/Output
Hardware STORE Busy (HSB).
When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
Power
Supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
V
CAP
NC
No Connect
No Connect.
This pin is not connected to the die.
Document #: 001-42879 Rev. *C
Page 3 of 24
[+] Feedb
PRELIMINARY
CY14B101LA, CY14B101NA
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. Refer to the
Truth Table For SRAM Operations
on
page 16 for a complete description of read and write modes.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
AutoStore
on page 6. In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 4
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to
DC Electrical
Characteristics
on page 8 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. Place a
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
Vcc
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0-16
or A
0-15
determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF
10kOhm
Vcc
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–15
are written into the memory if the data is valid t
SD
before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers t
HZWE
after WE goes LOW.
WE
V
CAP
V
SS
V
CAP
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB
[8]
pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after t
DELAY
. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
DELAY
) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101LA/CY14B101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
Page 4 of 24
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Document #: 001-42879 Rev. *C
[+] Feedb
PRELIMINARY
CY14B101LA, CY14B101NA
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14B101LA/CY14B101NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
STORE
cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
During this time, HSB is driven low by the HSB driver.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 2. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE, BHE, BLE
[3]
X
L
X
L
A
15
- A
0
[9]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Power
Standby
Active
Active
Active
[10]
Notes
9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A
14
- A
2
) are used to control software modes.
Rest of the address lines are don’t care.
10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-42879 Rev. *C
Page 5 of 24
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