CY7C1379C
9-Mbit (256K x 32) Flow-through SRAM
with NoBL™ Architecture
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 32 common I/O architecture
• Single 3.3V power supply (V
DD
)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non lead-free 165-Ball FBGA package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1379C is a 3.3V, 256K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1379C is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram–CY7C1379C (256K x 36)
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
Control
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05688 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 14, 2006
CY7C1379C
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
250
40
100 MHz
7.5
180
40
Unit
ns
mA
mA
Pin Configurations
100-Pin TQFP Pinout
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
NC(18M)
BW
D
BW
C
CEN
CLK
WE
OE
ADV/LD
A
A
82
A
100
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
BYTE C
BYTE D
NC
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
V
SS
/DNU
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
A
CY7C1379C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
NC
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
NC
BYTE B
BYTE A
39
40
41
42
A1
A0
NC
NC
43
V
SS
A
A
A
V
DD
A
A
A
NC(72M)
Document #: 38-05688 Rev. *D
NC(36M)
A
A
A
MODE
A
A
Page 2 of 15
CY7C1379C
Pin Configurations
(continued)
165-Ball FBGA Pinout
CY7C1379C (256K x 32)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
MODE
2
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/36M
3
CE
1
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BW
C
BW
D
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
5
BW
B
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
6
CE
3
CLK
7
CEN
WE
8
ADV/LD
OE
9
A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
11
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
NC
NC/288M
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
NC/144M NC/72M
A
A
Pin Definitions
Name
A
0
, A
1
, A
TQFP
37,36,32,33,34,3
5,44,45,46,
47,48,49,50,81,8
2,83,99,100
FBGA
R6,P6,A2,
A9,A10,B2
B10,P3,P4,
P8,P9,P10,
R3,R4,R8,
R9,R10,R11
B5,A5,A4,
B4
B7
I/O
Description
Input-
Address Inputs used to select one of the 256K address
Synchronous
locations.
Sampled at the rising edge of the CLK. A
[1:0]
are fed
to the two-bit burst counter.
BW
A
, BW
B
,
BW
C
, BW
D
WE
93,94,95,96
88
Input-
Byte Write Inputs, active LOW.
Qualified with WE to conduct
Synchronous writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Write Enable Input, active LOW.
Sampled on the rising edge
Synchronous of CLK if CEN is active LOW. This signal must be asserted LOW
to initiate a write sequence.
Input-
Advance/Load Input.
Used to advance the on-chip address
Synchronous counter or load a new address. When HIGH (and CEN is
asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order
to load a new address.
Input-Clock
Clock Input.
Used to capture all synchronous inputs to the
device. CLK is qualified with CEN. CLK is only recognized if CEN
is active LOW.
ADV/LD
85
A8
CLK
89
B6
CE
1
98
A3
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge
Synchronous of CLK. Used in conjunction with CE
2
, and CE
3
to select/deselect
the device.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge
Synchronous of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect
the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge
Synchronous of CLK. Used in conjunction with CE
1
and CE
2
to select/deselect
the device.
Page 3 of 15
CE
2
97
B3
CE
3
92
A6
Document #: 38-05688 Rev. *D
CY7C1379C
Pin Definitions
(continued)
Name
OE
TQFP
86
FBGA
B8
I/O
Description
Input-
Output Enable, asynchronous input, active LOW.
Combined
Asynchronous with the synchronous logic block inside the device to control the
direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the
data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been
deselected.
Input-
Clock Enable Input, active LOW.
When asserted LOW the
Synchronous Clock signal is recognized by the SRAM. When deasserted
HIGH the Clock signal is masked. Since deasserting CEN does
not deselect the device, CEN can be used to extend the previous
cycle when required.
Input-
ZZ “sleep” Input.
This active HIGH input places the device in a
Asynchronous non-time critical “sleep” condition with data integrity preserved.
For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
I/O-
Bidirectional Data I/O Lines.
As inputs, they feed into an
Synchronous on-chip data register that is triggered by the rising edge of CLK.
As outputs, they deliver the data contained in the memory
location specified by address during the clock rise of the Read
cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can
behave as outputs. When HIGH, DQ
s
are placed in a tri-state
condition. The outputs are automatically tri-stated during the
data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
CEN
87
A7
ZZ
64
H11
DQ
s
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
2,3,6,7,
8,9,12,13,
18,19,22,23,
24,25,28,29
M11,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,
F2,G2,J1,
K1,L1,M1,
J2,K2,L2
M2
R1
Mode
31
Input
Strap Pin
Mode Input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst sequence.
V
DD
15,41,65,91
D4,D8,E4,
E8,F4,F8,
G4,G8,H2,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
Power Supply
Power supply inputs to the core of the device.
V
DDQ
4,11,20,27,54,
61,70,77
I/O Power
Supply
Power supply for the I/O circuitry.
Document #: 38-05688 Rev. *D
Page 4 of 15
CY7C1379C
Pin Definitions
(continued)
Name
V
SS
TQFP
5,10,17,21,
26,40,55,60,
67,71,76,90,
FBGA
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,K
7,L5,L6,L7,M5
,M6,M7,
N4,N8
I/O
Ground
Ground for the device.
Description
NC
1,16,30,38,39,
A1,A11,B1,
42,43,51,66,80,8 B9,B11,C1,
4,95,96
C2,C10,C11,H
1,H3,H9,
H10,N1,N2,
N5,N6,N7
N10,N11,P1,P
2,P5,P7,
P11,R2,R5,
R7
14
-
–
No Connects.
Not Internally connected to the die.
18M, 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
V
SS
/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1379C has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs.
Page 5 of 15
Functional Overview
The CY7C1379C is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
CDV
) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW
[A:D]
can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
Document #: 38-05688 Rev. *D
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