CY62157BV18LL
ADVANCE INFORMATION
MoBL2™
512K x 16 Static RAM
Features
• Low voltage range:
— CY62157BV18LL: 1.65V–1.95V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
through I/O
15
) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), BHE
and BLE are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
18
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
truth table at the back of this datasheet for a complete descrip-
tion of read and write modes.
The CY62157BV18LL is available in a 48-Ball FBGA package.
Functional Description
The CY62157BV18LL is a high-performance CMOS static
RAM organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in por-
table applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduc-
es power consumption by 99% when addresses are not tog-
gling. The device can also be put into standby mode when
deselected (CE HIGH, CS2 LOW). The input/output pins (I/O
0
Logic Block Diagram
DATA IN DRIVERS
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
1024 X 4096
SENSE AMPS
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN DECODER
BHE
WE
CEx
OE
BLE
CEx is the combination of CE and CS2
62157V–1
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 23, 2000
ADVANCE INFORMATION
Pin Configuration
[1]
FBGA
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
Top View
4
3
A
0
A
3
A
5
A
17
V
SS
A
14
A
12
A
9
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CS2
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
CY62157BV18LL
MoBL2™
62146V–3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[2]
................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
................................. -0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Device
CY62157BV18
Range
Industrial
Ambient Temperature
–40°C to +85°C
V
CC
1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Product
Min.
CY62157BV18
1.65V
V
CC
Range
Typ.
[3]
Speed
Max.
1.95V
55, 70 ns
Operating (I
CC
)
Typ
[3]
Standby (I
SB2
)
Typ
[3]
Maximum
15 mA
Maximum
20
µA
1.8V
7 mA
2
µA
Notes:
1. NC pins are not connected to the die.
2. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
ADVANCE INFORMATION
Switching Characteristics
Over the Operating Range
[6]
55 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[7, 8]
WE HIGH to Low Z
[7]
5
55
40
40
0
0
40
25
0
20
10
70
60
60
0
0
50
30
0
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7, ]
OE HIGH to High Z
[8]
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CY62157BV18LL
MoBL2™
70 ns
Max.
Min.
70
55
70
10
55
25
70
35
5
20
25
10
20
25
0
55
55
70
70
5
20
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
Description
Min.
55
10
5
10
0
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
5
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, t
HZBE
is less than t
LZBE
, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
are specified for with C
L
=5 pF. Transition is measured ± 200 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
5
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