portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE are
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE
1
HIGH or
CE
2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE
1
LOW, CE
2
HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this
datasheet for a complete description of read and write modes.
Functional Description
[1]
The CY62157EV18 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
CE
2
CE
1
Power-Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
BHE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 38-05490 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 17, 2006
CY62157EV18
MoBL
®
Pin Configuration
[2]
FBGA
Top View
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
Vcc
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Product Portfolio
Product
Min.
CY62157EV18
1.65
V
CC
Range (V)
Typ.
[3]
1.8
Max.
2.25
45
Speed
(ns)
Power Dissipation
Operating I
CC
, (mA)
f = 1MHz
Typ.
[3]
1.8
Max.
3
f = f
max
Typ.
[3]
18
Max.
25
Standby, I
SB2
(µA)
Typ.
[3]
2
Max.
8
Notes:
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
Document #: 38-05490 Rev. *B
Page 2 of 11
CY62157EV18
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ..............................–0.2V to 2.45V (V
CCMAX
+ 0.2V)
DC Voltage Applied to Outputs
in High Z State
[4, 5]
..............–0.2V to 2.45V (V
CCMAX
+ 0.2V)
DC Input Voltage
[4, 5]
......... –0.2V to 2.45V (V
CCMAX
+ 0.2V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
–40°C to
+85°C
V
CC
[6]
1.65V to 2.25V
CY62157EV18LL Industrial
Electrical Characteristics
Over the Operating Range
45 ns
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
I
OL
= 0.1 mA
V
CC
= 1.65V to 2.25V
V
CC
= 1.65V to 2.25V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
Test Conditions
V
CC
= 1.65V
V
CC
= 1.65V
1.4
–0.2
–1
–1
18
1.8
2
Min.
1.4
0.2
V
CC
+ 0.2V
0.4
+1
+1
25
3
8
Typ.
[3]
Max.
Unit
V
V
V
V
µA
µA
mA
mA
µA
Output HIGH Voltage I
OH
= –0.1 mA
V
CC
Operating Supply f = f
MAX
= 1/t
RC
Current
f = 1 MHz
Automatic CE
Power-Down
Current — CMOS
Inputs
Automatic CE
Power-Down
Current — CMOS
Inputs
CE
1
> V
CC
−0.2V
or CE
2
< 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V)
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE, BHE and BLE),
V
CC
= V
CC
(max).
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC
(max).
I
SB2
2
8
µA
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
Notes:
4. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max.)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100
µs
ramp time from 0 to V
CC
(min) and 200
µs
wait time after V
CC
stabilization.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05490 Rev. *B
Page 3 of 11
CY62157EV18
MoBL
®
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[7]
Thermal Resistance
(Junction to Case)
[7]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
BGA
72
8.86
Unit
°C/W
°C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
R1
V
CC
10%
GND
R2 Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Value
13500
10800
6000
0.80
Data Retention Characteristics
[9]
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current V
CC
= V
DR
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery
Time
0
t
RC
Conditions
Min.
1.0
1
3
Typ.
[3]
Max.
Unit
V
µA
t
CDR[7]
t
R[8]
ns
ns
Data Retention Waveform
[9]
V
CC
,min.
t
CDR
DATA RETENTION MODE
V
DR
> 1.0 V
V
CC
,min.
t
R
V
CC
CE
1
or
BHE
.
BLE
or
CE2
Note:
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05490 Rev. *B
Page 4 of 11
CY62157EV18
MoBL
®
Switching Characteristics
Over the Operating Range
[10]
45 ns
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[13]
t
HZBE
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
[11, 12]
WE HIGH to Low-Z
[11]
10
45
35
35
0
0
35
35
25
0
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[11]
OE HIGH to High Z
[11, 12]
CE
1
LOW and CE
2
HIGH to Low Z
[11]
CE
1
HIGH and CE
2
LOW to High Z
[11, 12]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low
Z
[11]
5
18
BLE/BHE HIGH to HIGH Z
[11, 12]
0
45
45
10
18
5
18
10
45
22
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
12. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
13. If both byte enables are toggled together, this value is 10 ns.
14. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
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