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SY10EL16VDZGTR

产品描述LINE RECEIVER, PDSO16, 0.150 INCH, LEAD FREE, SOIC-16
产品类别模拟混合信号IC    驱动程序和接口   
文件大小139KB,共12页
制造商Micrel ( Microchip )
官网地址https://www.microchip.com
标准
下载文档 详细参数 全文预览

SY10EL16VDZGTR概述

LINE RECEIVER, PDSO16, 0.150 INCH, LEAD FREE, SOIC-16

SY10EL16VDZGTR规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Micrel ( Microchip )
零件包装代码SOIC
包装说明SOP,
针数16
Reach Compliance Codecompliant
ECCN代码EAR99
差分输出NO
输入特性DIFFERENTIAL
接口集成电路类型LINE RECEIVER
接口标准GENERAL PURPOSE
JESD-30 代码R-PDSO-G16
JESD-609代码e4
长度9.93 mm
湿度敏感等级1
标称负供电电压-3.3 V
功能数量1
端子数量16
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE
认证状态Not Qualified
最大接收延迟0.65 ns
接收器位数1
座面最大高度1.73 mm
表面贴装YES
技术ECL
温度等级INDUSTRIAL
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
宽度3.94 mm
Base Number Matches1

文档预览

下载PDF文档
Micrel, Inc.
ENHANCED
DIFFERENTIAL
RECEIVER
DESCRIPTION
SY10EL16VA-VF
SY100EL16VA-VF
SY10EL16VA-VF
SY100EL16VA-VF
FEATURES
s
3.3V and 5V power supply options
s
250ps propagation delay
s
Very high voltage gain vs. standard EL16 or EL16V
s
Ideal for Pulse Amplifier and Limiting Amplifier
applications
s
Data synchronous Enable/Disable (/EN) on Q
HG
and
/Q
HG
provides for complete glitchless gating of the
outputs
s
Ideal for gating timing signals
s
Complete solution for high quality, high frequency
crystal oscillator applications
s
Internal 75k
input pull-down resistors
s
Available in both 8- and 16-pin SOIC package; 8- and
10-pin (3mm) MSOP and in DIE form
PIN NAMES
Pin
D
Q
Q
HG
V
BB
/EN
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Enable Input
Function
TRUTH TABLE
/EN
0
1
Data
Logic Low
QHG Output
The SY10/100EL16VA-VF are differential receivers.
The devices are equivalent to SY10/100EL16 or SY10/
100EL16V with enhanced capabilities. The Q
HG
, /Q
HG
outputs have a DC gain several times larger than the DC
gain of the Q output.
The SY10/100EL16VA have an identical pinout to the
SY10/100EL16 or SY10/100EL16V. It provides a V
BB
output for either single-ended application or as a DC
bias for AC coupling to the device.
The SY10/100EL16VB are very similar to the SY10/
100EL16VA. The /Q output is provided for feedback
purposes.
The SY10/100EL16VC provides an /EN input which is
synchronized with the data input (D) signal in a way that
provides glitchless gating of the Q
HG
and /Q
HG
outputs. When
the /EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is
HIGH and the /EN goes HIGH, it will force the Q
HG
LOW and
the /Q
HG
HIGH on the next negative transition of the data
input. If the data input is LOW when the /EN goes HIGH, the
next data transition to a HIGH is ignored and Q
HG
remains
LOW and /Q
HG
remains HIGH. The next positive transition of
the data input is not passed on to the data outputs under these
conditions. The Q
HG
and /Q
HG
outputs remain in their dis-
abled state as long as the /EN input is held HIGH. The /EN
input has no influence on the /Q output and the data input is
passed on (inverted) to this output whether /EN is HIGH or
LOW. This configuration is ideal for crystal oscillator applica-
tions, where the oscillator can be free running and gated on
and off synchronously without adding extra counts to the
output.
The SY10/100EL16VD provides the flexibility of all the
combinations in DIE form, in 16-pin 150mil SOIC package or
in 10-pin MSOP package. The 16-pin SOIC and 10-pin MSOP
packages are ideal for prototyping DIE applications.
The SY10/100EL16VE are similar to the SY10/100EL16VB
where the Q, /Q output is made available differently. In this
package option, V
BB
is no longer provided.
The SY10/100EL16VF are similar to the SY10/100EL16VC,
offering the D, /D inputs rather than the V
BB
output.
M9999-052108
hbwhelp@micrel.com or (408) 955-1690
Rev.: Q
Amendment: /0
1
Issue Date: May 2008
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