Data Sheet
June 7, 2002
TRCV0110G 10 Gbits/s Limiting Amplifier
Clock Recovery, 1:16 Data Demultiplexer
Features
s
Applications
s
s
s
s
Integrated limiting amplifier with 7.5 mV sensitivity
at 1e-10 bit error rate (BER)
Integrated clock recovery and 1:16 data demulti-
plexer (deMUX)
Supports standard OC-192/STM-64 data rate of
9.9532 Gbits/s up through forward error correction
(FEC) rate of 10.709 Gbits/s as well as Ethernet
rate of 10.3 Gbits/s
Single 3.3 V power supply
Additional high-speed data input for system loop-
back operation
Standard low-voltage differential signaling (LVDS)
deMUX data and clock outputs
CMOS I/Os compatible with LVTTL signaling
Available in both 177-Ball CBGA (ceramic) and
FSBGA1 (plastic) packages
Jitter tolerance compliant with the following:
—
Telcordia Technologies™
GR-253 CORE
— ITU-T G.825
— ITU-T G.958
SONET/SDH optical modules
SONET/SDH line termination equipment
SONET/SDH test equipment
Ethernet 10 Gbit physical layer applications
s
s
Description
The Agere Systems Inc. TRCV0110G device
integrates a limiting amplifier combined with a clock
recovery circuit that feeds a data deMUX for use in
10 Gbits/s high-speed communications systems.
Additional features include an auxiliary clock output
and a reference clock input that can be either divided
by 16 or divided by 64. The TRCV0110G can be
operated within the standard OC192/STM64 data
rate of 9.9532 GHz and the FEC rate of
10.7092 Gbits/s.
s
s
s
s
s
s
TRCV0110G 10 Gbits/s Limiting Amplifier
Clock Recovery, 1:16 Data Demultiplexer
Data Sheet
June 7, 2002
Table of Contents
Contents
Page
Features .................................................................................................................................................................... 1
Applications ............................................................................................................................................................... 1
Description.................................................................................................................................................................1
Block Diagram......................................................................................................................................................... 3
Ball Information..........................................................................................................................................................4
Package Diagram ................................................................................................................................................... 4
Ball Assignments ....................................................................................................................................................5
Ball Description ....................................................................................................................................................... 7
Functional Overview ................................................................................................................................................11
FEC Rate Support ...................................................................................................................................................11
High-Speed Data Inputs ..........................................................................................................................................11
Limiting Amplifier Operation..................................................................................................................................11
Loopback Data Input.............................................................................................................................................12
Clock Recovery Operation.......................................................................................................................................12
CDR Input Jitter Tolerance ......................................................................................................................................13
Lock Detect..............................................................................................................................................................14
Demultiplexer Operation..........................................................................................................................................15
Demultiplexer Data Mute (MUTEDMXN) ..............................................................................................................15
CK622P/N Output Mute (MUTE622N) ..................................................................................................................15
CKOP/N Output Frequency Select (FREQCKO) ..................................................................................................15
CKOP/N Output Mute (MUTECKON) ...................................................................................................................15
Reset (RESETN)...................................................................................................................................................15
Absolute Maximum Ratings.....................................................................................................................................16
Handling Precautions ..............................................................................................................................................16
Recommended Operating Conditions .....................................................................................................................16
Electrical Characteristics .........................................................................................................................................17
LVDS, CMOS, and CML Input and Output Pins ...................................................................................................17
Timing Characteristics .............................................................................................................................................19
Output Timing .......................................................................................................................................................19
Output Timing .......................................................................................................................................................20
Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate).........................................................21
Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) .............................................................................21
Reference Frequency (REFCLKP/N, REFFREQ) (Ethernet Rate) .......................................................................21
Packaging Characteristics .......................................................................................................................................22
CBGA (Ceramic Ball Grid Array) Package Information.........................................................................................22
CBGA PWB Design Information ...........................................................................................................................22
CBGA Assembly Information ................................................................................................................................23
CBGA Suggested Underfill Process .....................................................................................................................24
CBGA Reference Materials...................................................................................................................................24
Package Diagram—177-Ball CBGA (Bottom View) ..............................................................................................25
FSBGA1 Package Information ..............................................................................................................................26
FSBGA1 PWB Design Information .......................................................................................................................26
FSBGA1 Assembly Information ............................................................................................................................26
FSBGA1 Reference Materials...............................................................................................................................27
Package Diagram—177-Ball FSBGA1 (Bottom View) ..........................................................................................28
Ordering Information................................................................................................................................................29
2
Agere Systems Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
