ASM1232LP/LPS
5V
μP
Power Supply Monitor
and Reset Circuit
General Description
The ASM1232LP/LPS is a fully integrated microprocessor
Supervisor. It can halt and restart a “hung-up”
microprocessor, restart a microprocessor after a power
failure. It has a watchdog timer and external reset
override.
A precision temperature-compensated reference and
comparator circuits monitor the 5V, V
CC
input voltage
status. During power-up or when the V
CC
power supply
falls outside selectable tolerance limits, both RESET and
RESET become active. When V
CC
rises above the
threshold voltage, the reset signals remain active for an
additional 250ms minimum, allowing the power supply
and system microprocessor to stabilize. The trip point
tolerance signal, TOL, selects the trip level tolerance to
be either 5% or 10%.
Each device has both a push-pull, active HIGH reset
output and an open drain active LOW reset output. A
debounced manual reset input, PBRST, activates the
reset outputs for a minimum period of 250ms.
There is a watchdog timer to stop and restart a
microprocessor that is “hung-up”. The watchdog timeouts
periods are selectable: 150ms, 610ms and 1200ms. If the
ST input is not strobed LOW before the time-out period
expires, a reset is generated.
Devices are available in 8-pin DIP, 16-pin SO and
compact 8-pin MicroSO packages.
Key Features
5V supply monitor
Selectable watchdog period
Debounce manual push-button reset input
Precision temperature-compensated voltage
reference and comparator.
Power-up, power-down and brown out detection
250ms minimum reset time
Active LOW open drain reset output and active HIGH
push-pull output
Selectable trip point tolerance: 5% or 10%
Low-cost surface mount packages: 8-pin/16-pin SO,
8-pin DIP and 8-pin Micro SO packages
Wide operating temperature -40°C to +85°C (N
suffixed devices)
Applications
Microprocessor Systems
Computers
Controllers
Portable Equipment
Intelligent Instruments
Automotive Systems
©2010 SCILLC. All rights reserved.
JANUARY 2010 – Rev. 2
Publication Order Number:
ASM1232/D
ASM1232LP/LPS
Typical Operating Circuit
Block Diagram
Rev. 2 | Page 2 of 13 | www.onsemi.com
ASM1232LP/LPS
Pin Configuration
Pin Description
Pin #
8-Pin Package
1
2
3
4
Pin #
16-Pin Package
2
4
6
8
Pin
Name
PBRST
T
D
T
OL
GND
Function
Debounced manual pushbutton RESET input.
Watchdog time delay selection. (t
TD
= 150ms for T
D
= GND, t
TD
= 610ms
for T
D
=Open, and t
TD
= 1200ms for T
D
= V
CC
).
Selects 5% (T
OL
connected to GND) or 10% (T
OL
connected to V
CC
) trip
point tolerance.
Ground.
Active HIGH reset output. RESET is active:
1. If V
CC
falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by T
D
expires.
4. During power-up.
5
9
RESET
6
7
8
11
13
15
1,3,5,7,
10,12,14,16
RESET
ST
V
CC
NC
Active LOW reset output. (See RESET).
Strobe input.
5V power.
No internal connection.
Rev. 2 | Page 3 of 13 | www.onsemi.com
ASM1232LP/LPS
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or
micro controller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push-pull output stage and is the logical opposite to
RESET.
RESET is an active LOW signal. It is developed with an
open drain driver. A pull up resistor of typical value 10kΩ
to 50kΩ is required to connect with the output.
Trip Point Tolerance Selection
The TOL input is used to determine the level V
CC
can vary
below 5V without asserting a reset. With TOL connected
to V
CC
, RESET and RESET become active whenever V
CC
falls below 4.5V. RESET and RESET become active
when the V
CC
falls below 4.75V if TOL is connected to
ground.
After V
CC
has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250ms. On power-down, once V
CC
falls below
the reset threshold RESET stays LOW and is guaranteed
to be 0.4V or less until V
CC
drops below 1.2V. The active
HIGH reset signal is valid down to a V
CC
level of 1.2V
also.
Tolerance
Select
TOL = V
CC
TOL = GND
Tolerance
Min
10%
5%
4.25
4.5
TRIP Point Voltage
(V)
Nom
4.37
4.62
Max
4.49
4.74
Rev. 2 | Page 4 of 13 | www.onsemi.com
ASM1232LP/LPS
Application Information
Manual Reset Operation
Push-button switch input, PBRST, allows the user to
override the internal trip point detection circuits and issue
reset signals. The pushbutton input is debounced and is
pulled HIGH through an internal 40kΩ resistor.
When PBRST is held LOW for the minimum time t
PB
, both
resets become active and remain active for a minimum
time period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is
required, since PBRST is pulled HIGH by an internal
40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line
or shorted to ground with a mechanical switch.
Rev. 2 | Page 5 of 13 | www.onsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
