74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 6 August 2009
Product data sheet
1. General description
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and
V
CC(B)
can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to V
CC(A)
and pins nBn are referenced to
V
CC(B)
. A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
I
Wide supply voltage range:
N
V
CC(A)
: 0.8 V to 3.6 V
N
V
CC(B)
: 0.8 V to 3.6 V
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3B exceeds 8000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Maximum data rates:
N
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
I
I
I
I
I
I
I
N
200 Mbit/s (≥ 1.1 V to 3.3 V translation)
N
200 Mbit/s (≥ 1.1 V to 2.5 V translation)
N
200 Mbit/s (≥ 1.1 V to 1.8 V translation)
N
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
N
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVCH4T245D
−40 °C
to +125
°C
SO16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
74AVCH4T245PW
−40 °C
to +125
°C
74AVCH4T245BQ
−40 °C
to +125
°C
DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
13
1B1
V
CC(A)
V
CC(B)
12
1B2
11
2B1
10
2B2
15
1OE
2OE
14
2
1DIR
2DIR
3
1A1
4
5
1A2
6
2A1
7
2A2
001aak280
Fig 1.
Logic symbol
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
2 of 26
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
DIR
OE
A1
B1
A2
B2
V
CC(A)
V
CC(B)
001aak281
Fig 2.
Logic diagram (one 2-bit transceiver)
5. Pinning information
5.1 Pinning
74AVCH4T245
V
CC(A)
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
1
2
3
4
5
6
7
8
001aak288
16 V
CC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9
GND
Fig 3. Pin configuration SOT109-1 (SO16)
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
3 of 26
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
74AVCH4T245
V
CC(A)
2
3
4
5
6
7
8
GND
GND
9
GND
(1)
1
terminal 1
index area
16 V
CC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
74AVCH4T245
V
CC(A)
1DIR
2DIR
1A1
1A2
2A1
2A2
GND
1
2
3
4
5
6
7
8
001aak287
1DIR
16 V
CC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9
GND
2DIR
1A1
1A2
2A1
2A2
001aak289
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SOT403-1 (TSSOP16)
Fig 5. Pin configuration SOT763-1 (DHVQFN16)
5.2 Pin description
Table 2.
Symbol
V
CC(A)
1DIR, 2DIR
1A1, 1A2
2A1, 2A2
GND
[1]
2B2, 2B1
1B2, 1B1
2OE, 1OE
V
CC(B)
[1]
Pin description
Pin
1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16
Description
supply voltage A (nAn, nOE and nDIR inputs are referenced to V
CC(A)
)
direction control
data input or output
data input or output
ground (0 V)
data input or output
data input or output
output enable input (active LOW)
supply voltage B (nBn inputs are referenced to V
CC(B)
)
All GND pins must be connected to ground (0 V).
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
4 of 26
NXP Semiconductors
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
nOE
[2]
L
L
H
X
nDIR
[2]
L
H
X
X
Input/output
[3]
nAn
[2]
nAn = nBn
input
Z
Z
nBn
[2]
input
nBn = nAn
Z
Z
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The nAn, nDIR and nOE input circuit is referenced to V
CC(A)
; The nBn input circuit is referenced to V
CC(B)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[4]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+4.6
+4.6
-
+4.6
-
V
CCO
+ 0.5
+4.6
±50
100
-
+150
500
Unit
V
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
I
< 0 V
[1]
−50
−0.5
−50
[1][2][3]
[1]
[2]
V
O
< 0 V
Active mode
Suspend or 3-state mode
V
O
= 0 V to V
CCO
I
CC(A)
or I
CC(B)
−0.5
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[4]
-
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with the output port.
V
CCO
+ 0.5 V should not exceed 4.6 V.
For SO16 package: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP16 package: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN16 package: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
5 of 26
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