October 2007
HYS64T32x00EDL–[25F/…/3.7]–B2
HYS64T64x20EDL–[25F/…/3.7]–B2
HYS64T128x21EDL–[25F/…/3.7]B2
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
RoHs Compliant Products
Internet Data Sheet
Rev. 1.13
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
HYS64T32x00EDL–[25F/…/3.7]–B2, HYS64T64x20EDL–[25F/…/3.7]–B2, HYS64T128x21EDL–[25F/…/3.7]B2
Revision History: 2007-10, Rev. 1.13
Page
5-11
16, 17, 23
All
All
4
Subjects (major changes since last revision)
Editorial change and adapted to internet edition
Technical Change, Figure updated
Editorial change
Updated HYS64T[32/64/128]9xxEDL–[25F/.../3.7](–)B2
Table 2 corrected product string to 21 digits
Previous revision 1.11, 2007-09
Previous revision 1.11, 2007-08
Previous revision 1.1, 2007-01
Previous revision 1.0, 2006-10
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Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
08212006-PKYN-2H1B
2
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 200-pin small-outline DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm
wide
Based on standard reference layouts Raw Cards 'A', 'C'
and 'E'
RoHS compliant products
1)
• 200-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
• 128M
×
64, 32M
×
64, 64M
×
64 module organization, and
32M
×
16, 64M
×
8 chip organization
• 1GB, 512MB, 256MB Modules built with 512MBit DDR2
SDRAMs in PG-TFBGA-60 and PG-TFBGA-84 chipsize
packages .
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
1)
Min. Row Cycle Time
DDR2
PC2
–25F
–800D
–6400D
5–5–5
–2.5
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
–3
–667C
–5300C
4–4–4
200
333
333
–
12
12
45
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
60
–3.7
–533C
–4200C
4–4–4
200
266
266
–
15
15
45
60
Unit
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
57.5
60
57
1) Product released after 01-08-2007 will support
t
RAS
= 40 ns for all DDR2 speed sort.
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RC
200
266
400
–
12.5
12.5
45
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.13, 2007-10
08212006-PKYN-2H1B
3
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1.2
Description
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
module family are small-outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules
in128M
×
64 (1GB),
32M
×
64 (256MB), 64M
×
64 (512MB) in organization and
density, intended for mounting into 200-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2-6400-555
HYS64T128921EDL–25FB2
HYS64T64920EDL–25F–B2
HYS64T32900EDL–25F–B2
HYS64T128021EDL–25FB2
HYS64T64020EDL–25F–B2
HYS64T32000EDL–25F–B2
PC2-6400-666
HYS64T128921EDL–2.5B2
HYS64T64920EDL–2.5–B2
HYS64T32900EDL–2.5–B2
HYS64T128021EDL–2.5B2
HYS64T64020EDL–2.5–B2
HYS64T32000EDL–2.5–B2
PC2-5300-444
HYS64T128921EDL–3–B2
HYS64T64920EDL–3–B2
HYS64T32900EDL–3–B2
HYS64T128021EDL–3–B2
HYS64T64020EDL–3–B2
HYS64T32000EDL–3–B2
PC2-5300-555
HYS64T128921EDL–3S–B2
HYS64T64920EDL–3S–B2
HYS64T32900EDL–3S–B2
HYS64T128021EDL–3S–B2
HYS64T64020EDL–3S–B2
HYS64T32000EDL–3S–B2
1GB 2R×8 PC2–5300S–555–12–E0
512MB 2R×16 PC2–5300S–555–12–A0
256MB 1R×16 PC2–5300S–555–12–C0
1GB 2R×8 PC2–5300S–555–12–E0
512MB 2R×16 PC2–5300S–555–12–A0
256MB 1R×16 PC2–5300S–555–12–C0
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1GB 2R×8 PC2–5300S–444–12–E0
512MB 2R×16 PC2–5300S–444–12–A0
256MB 1R×16 PC2–5300S–444–12–C0
1GB 2R×8 PC2–5300S–444–12–E0
512MB 2R×16 PC2–5300S–444–12–A0
256MB 1R×16 PC2–5300S–444–12–C0
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1GB 2R×8 PC2–6400S–666–12–E0
512MB 2R×16 PC2–6400S–666–12–A0
256MB 1R×16 PC2–6400S–666–12–C0
1GB 2R×8 PC2–6400S–666–12–E0
512MB 2R×16 PC2–6400S–666–12–A0
256MB 1R×16 PC2–6400S–666–12–C0
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1GB 2R×8 PC2–6400S–555–12–E0
512MB 2R×16 PC2–6400S–555–12–A0
256MB 1R×16 PC2–6400S–555–12–C0
1GB 2R×8 PC2–6400S–555–12–E0
512MB 2R×16 PC2–6400S–555–12–A0
256MB 1R×16 PC2–6400S–555–12–C0
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
Compliance Code
2)
Description
SDRAM Technology
Rev. 1.13, 2007-10
08212006-PKYN-2H1B
4
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
1)
PC2-4200-444
HYS64T128921EDL–3.7B2
HYS64T64920EDL–3.7–B2
HYS64T32900EDL–3.7–B2
HYS64T128021EDL–3.7B2
HYS64T64020EDL–3.7–B2
HYS64T32000EDL–3.7–B2
Compliance Code
2)
1GB 2R×8 PC2–4200S–444–12–E0
512MB 2R×16 PC2–4200S–444–12–A0
256MB 1R×16 PC2–4200S–444–12–C0
1GB 2R×8 PC2–4200S–444–12–E0
512MB 2R×16 PC2–4200S–444–12–A0
256MB 1R×16 PC2–4200S–444–12–C0
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
1 Rank, Non-ECC
SDRAM Technology
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–E0" where 6400S
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card "E".
TABLE 3
Address Format
DIMM
Density
1GB
512MB
256MB
Module
Organization
128M
×
64
64M
×
64
32M
×
64
Memory
Ranks
2
2
1
ECC/
Non-ECC
Non-ECC
Non-ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
16
8
4
14/2/10
13/2/10
13/2/10
Raw
Card
E
A
C
TABLE 4
Components on Modules
Product Type
1)2)
HYS64T128921EDL
HYS64T128021EDL
HYS64T64920EDL
HYS64T64020EDL
HYS64T32900EDL
HYS64T32000EDL
DRAM Components
1)
HYB18T512800B2F
HYB18T512800B2F
HYB18T512160B2F
HYB18T512160B2F
HYB18T512160B2F
HYB18T512160B2F
DRAM Density
512Mbit
512Mbit
512Mbit
512Mbit
512Mbit
512Mbit
DRAM Organisation
64M
×
8
64M
×
8
32M
×
16
32M
×
16
32M
×
16
32M
×
16
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.13, 2007-10
08212006-PKYN-2H1B
5
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