Datasheet> 器件分类 > 存储> 存储> IS61DDB451236A-250B4

文档预览

IS61DDB451236A-250B4: 产品描述DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165; 产品类别存储存储; 文件大小483KB，共30页; 制造商Integrated Silicon Solution ( ISSI )

下载文档详细参数全文预览

IS61DDB451236A-250B4概述

DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LFBGA-165

IS61DDB451236A-250B4规格参数

参数名称	属性值
厂商名称	Integrated Silicon Solution ( ISSI )
零件包装代码	BGA
包装说明	LBGA,
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	0.45 ns
其他特性	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B165
长度	15 mm
内存密度	18874368 bit
内存集成电路类型	DDR SRAM
内存宽度	36
功能数量	1
端子数量	165
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	512KX36
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
座面最大高度	1.4 mm
最大供电电压 (Vsup)	1.89 V
最小供电电压 (Vsup)	1.71 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	13 mm
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

IS61DDB41M18A

IS61DDB451236A

1Mx18, 512Kx36

18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

FEATURES



512Kx36 and 1Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid

window.

Common I/O read and write ports.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and

write input ports.

Fixed 4-bit burst for read and write operations.

Clock stop support.

Two input clocks (K and K#) for address and control

registering at rising edges only.

Two input clocks (C and C#) for data output control.

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

+1.8V core power supply and 1.5V to1.8V VDDQ,

used with 0.75V to 0.9V VREF.

HSTL input and output interface.

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x

user-supplied precision resistor.

ADVANCED INFORMATION

JULY 2012

DESCRIPTION

The 18Mb IS61DDB451236A and IS61DDB41M18A are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have a common I/O

bus. The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed. Refer to

the

Timing Reference Diagram for Truth Table

for a

description of the basic operations of these DDR-II (Burst of

4) CIO SRAMs.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.

The following are registered internally on the rising edge of

the K clock:



Read/write address



Read enable



Write enable



Byte writes for burst addresses first and third



Data-in for burst addresses first and third

The following are registered on the rising edge of the K#

clock:



Byte writes for burst addresses second and fourth



Data-in for burst addresses second and fourth

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the

second and third rising edges of the C# clock (starting on and

half cycles later after read command). The data-outs from the

second and fourth bursts are updated with the third and

fourth rising edges of the C clock. The K and K# clocks are

used to time the data-outs whenever the C and C# clocks are

tied high. Two full clock cycles are required to complete a

read operation.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.



without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

IS61DDB41M18A

IS61DDB451236A

Ball Description

Symbol

K, K#

Type

Input

Description

Input clock: This input clock pair registers address and control inputs on the rising edge of K, and

registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of

phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

These balls cannot remain VREF level.

Input clock for output data. C and C# are used to clock out the READ data. They can be used

together to deskew the flight times of various devices on the board back to the controller. See

application example for further details.

Synchronous echo clock outputs: The edges of these outputs are tightly matched to the

synchronous data outputs and can be used as a data valid indication. These signals are free running

clocks and do not stop when Q tri-states.

DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the

previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock

time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the

device can be operated at a frequency of up to 167 MHz.

Synchronous address inputs: These inputs are registered and must meet the setup and hold times

around the rising edge of K. These inputs are ignored when device is deselected.

Data input and output signals. Input data must meet setup and hold times around the rising edges of

K and K# during WRITE operations. These pins drive out the requested data when the read

operation is active. Valid output data is synchronized to the respective C and C#, or to the

respective K and K# if C and /C are tied to high. When read access is deselected, DQ0 - DQn are

automatically tri-stated.

See BALL CONFIGURATION figures for ball site location of individual signals.

The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.

The x36 device uses DQ0~DQ35.

Synchronous Read or Write input. When LD# is low, this input designates the access type (read

when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times

around edge of K.

Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition

includes address and read/write direction.

Synchronous byte writes: When low, these inputs cause their respective byte to be registered and

written during WRITE cycles. These signals are sampled on the same edge as the corresponding

data and must meet setup and hold times around the rising edges of K and #K for each of the two

rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffers.

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating

Conditions for range.

Ground of the device

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. DQ and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this

ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance

mode. This ball cannot be connected directly to VSS or left unconnected.

IEEE1149.1 input pins for JTAG.

IEEE1149.1 output pins for JTAG.

No connect: These signals should be left floating or connected to ground to improve package heat

dissipation.

C, C#

CQ, CQ#

Input

Output

Doff#

Input

DQ0 - DQn

Bidir

R/W#

LD#

REF

DDQ

TMS, TDI,

TCK

TDO

Input

reference

Power

Ground

Input

Output

N/A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

IS61DDB41M18A

IS61DDB451236A

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is

presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write

burst address follows next, registered by the rising edge of K#. The third data-out is clocked by the subsequent rising

edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of the K# clock.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array

on the third write cycle. A read cycle to the last two write address produces data from the write buffers. The SRAM

maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written (see

X18/X36 Write Truth Tables

and

Timing Reference Diagram for Truth Table).

Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM to adjust

its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the

SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee

impedance matching is between 175Ω and 350Ω at V

DDQ

=1.5V. The RQ resistor should be placed less than two inches

away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ should not be

connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in

supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances

values. The final impedance value is achieved within 1024clock cycles.

Clock Consideration

This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to

minimize power and requires only 1024 cycles to restart. No clocks can be issued until V

reaches its allowable

operating range.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up

and must never change. Under this condition, K and K# control the output timings. Either clock pair must have both

polarities switching and must never connect to V

REF

, as they are not differential clocks.

Delay Locked Loop (DLL)

Delay Lock Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to enhance

the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match the clock

frequency. Therefore device can have stable output over the temperature and voltage variation.

DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the

AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL

off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy

QUAD mode.

The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#

for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is

not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being

reset, it gets locked after 2048 cycles of stable clock.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

IS61DDB451236A-250B4

IS61DDB451236A-250B4概述

IS61DDB451236A-250B4规格参数

文档预览

推荐资源