1-Line To 10-Line Clock Driver With 3-State Outputs
Features
•
•
•
•
Low Output Skew, Low Pulse Skew for Clock-
Distribution and Clock-Generation Applications.
Operates at 3.3V Supply Voltage
.
LVTTL-Compatible Inputs and Outputs.
Supports Mixed-Mode Signal Operation.
(5V Input and Output Voltages With 3.3V Supply
Voltage).
•
•
•
•
Distributes One Clock Input to Ten Outputs.
Outputs have Internal Series Damping Resistor
to Reduce Transmission Line Effects.
Distributed
V
CC
and
Ground
Pins
Reduce
Switching Noise.
Package Options Include Plastic Small-Outline
and Shrink Small-Outline Packages.
Product Description
The ASM2P2351AH is a high-performance clock-driver
circuit that distributes one input (A) to ten outputs (Y)
with minimum skew for clock distribution. The output-
enable (OE) input disables the outputs to a high-
impedance state. Each output has an internal series
damping resistor to improve signal integrity at the load.
The ASM2P2351AH operates at nominal 3.3V Supply
Voltage.
The propagation delays are adjusted at the factory
using the P0 and P1 pins. The factory adjustments
ensure that the part-to-part skew is minimized and is
kept within a specified window. Pins P0 and P1 are not
intended for customer use and should be connected to
GND.
The ASM2P2351AH is characterized for operation
from 0
°
C to 70
°
C.
Pin Configuration
Logic Diagram (Positive Logic)
5
OE
23
21
19
18
6
A
7 8
PO P1
16
14
11
9
4
Y1
Y2
Y3
GND
Y10
V
CC
Y9
OE
Y4
Y5
Y6
Y7
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
GND
Y1
V
CC
Y2
GND
Y3
Y4
GND
Y5
V
CC
Y6
GND
A
P0
P1
Y8
V
CC
ASM2P2351AH
19
18
17
16
15
14
13
Y8
Y9
Y7
GND
2
Y10
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ASM2P2351AH
Pin Name
GND
Y10
V
CC
Y9
OE
A
P0
P1
Y8
V
CC
Y7
GND
GND
Y6
V
CC
Y5
GND
Y4
Y3
GND
Y2
V
CC
Y1
GND
Typ
P
O
P
O
I
I
-
-
O
P
O
P
P
O
P
O
P
O
O
P
O
P
O
P
Ground Pin
Output 10
Power Supply Pin
Output 9
Description
Output Enable Pin. When this pin is low, the outputs Y[1:10] are enabled
and when this pin is high , the outputs Y[1:10] are disabled.
Input Clock
No Connect
No Connect
Output 8
Power Supply
Output 7
Ground Pin
Ground Pin
Output 6
Power Supply
Output 5
Ground Pin
Output 4
Output 3
Ground Pin
Output 2
Power Supply
Output 1
Ground Pin
Function Table
Inputs
A
L
H
L
H
Outputs
OE
H
H
L
L
In
Z
Z
L
H
1-Line To 10-Line Clock Driver With 3-State Outputs
Notice: The information in this document is subject to change without notice.
2 of 12
November 2006
rev 0.3
Absolute Maximum Ratings
Symbol
V
CC
V
IN
t
STG
t
A
t
s
t
J
t
DV
ASM2P2351AH
Parameter
Voltage on Supply pin with respect to Ground
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Rating
-0.5 to +4.6
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Recommended operating conditions
(see Note 3)
Symbol
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
f
clock
T
A
.
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input clock frequency
Operating free air temperature
Min
3
2
0
Max
3.6
0.8
5.5
–12
12
100
70
Unit
V
V
V
V
mA
mA
MHz
°C
0
NOTE 3: Unused pins (input or I/O) must be held high or low.
Electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
Parameter
V
IK
V
OH
V
OL
I
I
I
O
1
Test Conditions
V
CC
= 3 V,
V
CC
= 3 V,
V
CC
= 3 V,
V
CC
= 3.6 V,
V
CC
= 3.6 V,
V
CC
= 3.6 V,
I
I
= –18 mA
I
OH
= – 12 mA
I
OL
= 12 mA
V
I
= V
CC
or GND
V
O
= 2.5 V
V
CC
= 3 V
Outputs high
V
I
= V
CC
or GND
V
CC
= 3.3 V,
V
CC
= 3.3 V,
Outputs low
Outputs disabled
f = 10 MHz
f = 10 MHz
Min
2
Typ
Max
-1.2
0.8
±1
Unit
V
V
V
mA
mA
mA
mA
pF
pF
-7
-70
± 10
0.3
15
0.3
4
6
I
OZ
I
CC
C
i
C
o
V
CC
= 3.6 V, I
O
= 0,
V
I
= V
CC
or GND,
V
O
= V
CC
or GND,
Note: 1 Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
1-Line To 10-Line Clock Driver With 3-State Outputs
Notice: The information in this document is subject to change without notice.
3 of 12
November 2006
rev 0.3
Switching Characteristics,
C
L
= 50 pF (see Figures 1 and 2)
From
(Input)
To
(Output)
ASM2P2351A
V
CC
= 3.3 V, TA = 25°C
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
t
sk(p)
t
sk(pr)
t
r
t
f
A
OE
OE
A
A
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
3.8
3.6
2.4
2.4
2.2
2.2
ASM2P2351AH
Parameter
Typ
4.3
4.1
4.9
4.3
4.4
4.6
0.3
0.2
Max
4.8
4.6
6.0
6.0
6.3
6.3
0.5
0.8
1
ASM2P2351AH
V
CC
= 3 V to 3.6 V,
T
A
= 0°C to 70°C
Min
Max
Unit
nS
1.8
1.8
2.1
2.1
6.9
6.9
7.1
7.3
0.5
0.8
1
2.5
2.5
nS
nS
nS
nS
nS
nS
nS
Switching Characteristics temperature and V
CC
coefficients over recommended operating free-air
temperature and V
CC
range
(see Note 3)
From
To
Parameter
Min
Max
Unit
(Input) (Output)
t
PLH
(T)
t
PHL
(T)
t
PLH
(V
CC
)
t
PHL
(V
CC
)
Average temperature coefficient of low to high
propagation delay
Average temperature coefficient of high to low
propagation delay
Average V
CC
coefficient of low to high propagation
delay
Average V
CC
coefficient of high to low propagation
delay
A
A
A
A
Y
Y
Y
Y
85
1
50
1
pS/10°C
pS/10°C
pS/ 100
mV
pS/ 100
mV
-145
2
-100
2
Note: 1 t
PLH
(T) and t
PHL
(T) are virtually independent of V
CC
.
2 t
PLH
(V
CC
) and t
PHL
(V
CC
) are virtually independent of temperature.
3 This data was extracted from characterization material and are not tested at the factory.
1-Line To 10-Line Clock Driver With 3-State Outputs
Notice: The information in this document is subject to change without notice.
4 of 12
November 2006
rev 0.3
Parameter Measurement Information
500Ω
S1
6V
OPEN
GND
ASM2P2351AH
From Output
Under Test
C
L
= 50pF
(see Note A)
500Ω
LOAD CIRCUIT
3V
TIMING INPUT
1.5V
OV
t
su
t
h
3V
1.5V
DATA INPUT
1.5V
3V
1.5V
INPUT
t
PLH
t
PHL
2V
1.5V
OUTPUT
0.8V
t
r
t
r
0.8V
V
OL
V
OH
2V
1.5V
OV
t
W
3V
INPUT
1.5V
1.5V
OV
1-Line To 10-Line Clock Driver With 3-State Outputs
Notice: The information in this document is subject to change without notice.
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