March 2008
HYS72T1Gx42EP–[25F/2.5]–C
HYS72T1Gx42EP–[3/3S/3.7]–C
240-Pin Dual Die Registered DDR2 SDRAM Modules
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.20
Internet Data Sheet
HYS72T1Gx42EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
HYS72T1Gx42EP–[25F/2.5]–C, HYS72T1Gx42EP–[3/3S/3.7]–C
Revision History: 2008-03, Rev. 1.20
Page
All
All
All
Subjects (major changes since last revision)
Added product type HYS72T1G442EP-25F-C and adapted to internet edition.
Added product type HYS72T1G442EP-3S-C and adapted to internet edition.
New Document and adapted to internet edition.
Previous Revision: 2007-07, Rev. 1.0
Previous Revision: 2007-07, Rev. 1.0
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Your feedback will help us to continuously improve the quality of this document.
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qag_techdoc_A4, 4.20, 2008-01-25
07242007-LR08-OZC0
2
Internet Data Sheet
HYS72T1Gx42EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM modules product family with parity bit for address and
control bus and describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
Serial Presence Detect with E
2
PROM.
Dimensions (nominal): 30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Cards 'Z'.
RoHS compliant products
1)
.
• 240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
• Four rank 1024M
×
72 module organization, and
2
×256M ×
4 chip organization.
• 8GB Modules built with stacked 2Gbit (1Gbit Dual Dies)
DDR2 SDRAMs in PG-TFBGA-63 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
DDR2
PC2
–25F
–800D
–6400D
5–5–5
–2.5
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
–3
–667C
–5300C
4–4–4
200
333
333
–
12
12
45
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
–3.7
–533C
–4200C
4–4–4
200
266
266
–
15
15
45
Unit
Note
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
200
266
400
–
12.5
12.5
45
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 1.20, 2008-03
07242007-LR08-OZC0
3
Internet Data Sheet
HYS72T1Gx42EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2
PC2
–25F
–800D
–6400D
5–5–5
57.5
15
–2.5
–800E
–6400E
6–6–6
60
17.5
–3
–667C
–5300C
4–4–4
57
15
–3S
–667D
–5300D
5–5–5
60
18
–3.7
–533C
–4200C
4–4–4
60
18.75
Unit
Note
t
CK
ns
ns
1)2)
t
RC
Precharge-All (8 banks) command
t
PREA
Min. Row Cycle Time
period
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
1.2
Description
All control and address signals are re-driven on the DIMM
using register devices and a PLL for the clock distribution.
This reduces capacitive loading to the system bus, but adds
one cycle to the SDRAM timing. Decoupling capacitors are
mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the
2-pin I
2
C protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
The
Qimonda
HYS72T1Gx42EP–[25F/2.5/3/3S/3.7]–C
module family are Registered DIMM modules “RDIMMs” with
parity bit for address and control bus and 30 mm height based
on DDR2 technology.
DIMMs are available as ECC modules in 1024M
×
72 (8GB)
in organization and density, intended for mounting into 240-
pin connector sockets.
The memory array is designed with stacked 2Gbit (1Gbit Dual
Dies) Double-Data-Rate-Two (DDR2) Synchronous DRAMs.
TABLE 2
Ordering Information for Modules without heat sink
Product Type
1)
PC2-6400 (5-5-5)
HYS72T1G242EP-25F-C
PC2-6400 (6-6-6)
HYS72T1G242EP-2.5-C
PC2-5300 (4-4-4)
HYS72T1G242EP-3-C
PC2-5300 (5-5-5)
HYS72T1G242EP-3S-C
PC2-4200 (4-4-4)
HYS72T1G242EP-3.7-C
8GB 4R×4 PC2–4200P–444–12–ZZ
4 Ranks, ECC
1Gbit (×4)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–ZZ" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the JEDEC SPD Revision 1.2 and produced
on the Raw Card "Z".
Compliance Code
2)
8GB 4R×4 PC2–6400P–555–12–ZZ
8GB 4R×4 PC2–6400P–666–12–ZZ
8GB 4R×4 PC2–5300P–444–12–ZZ
8GB 4R×4 PC2–5300P–555–12–ZZ
Description
4 Ranks, ECC
4 Ranks, ECC
4 Ranks, ECC
4 Ranks, ECC
SDRAM Technology
1Gbit (×4)
1Gbit (×4)
1Gbit (×4)
1Gbit (×4)
Rev. 1.20, 2008-03
07242007-LR08-OZC0
4
Internet Data Sheet
HYS72T1Gx42EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
TABLE 3
Ordering Information for Modules with heat sink
Product Type
1)
PC2-6400 (5-5-5)
HYS72T1G442EP-25F-C
PC2-5300 (5-5-5)
HYS72T1G442EP-3S-C
8GB 4R×4 PC2–5300P–555–12–ZZ
4 Ranks, ECC
1Gbit (×4)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–ZZ" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the JEDEC SPD Revision 1.2 and produced
on the Raw Card "Z".
Compliance Code
2)
8GB 4R×4 PC2–6400P–555–12–ZZ
Description
4 Ranks, ECC
SDRAM Technology
1Gbit (×4)
TABLE 4
Address Format
DIMM
Density
8GB
Module
Organization
1024M
×
72
Memory
Ranks
4
ECC/
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
36 DDP
1)
14/3/11
Raw
Card
Z
1) DDP Dual Die Package
TABLE 5
Components on Modules
Product Type
1)2)
HYS72T1G442EP
HYS72T1G242EP
DRAM Components
1)
HYB18T2G402CF
HYB18T2G402CF
DRAM Density
2
×1Gbit
2
×1Gbit
DRAM Organisation
2
×256M ×
4
2
×256M ×
4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.20, 2008-03
07242007-LR08-OZC0
5
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