HYB25D512400A/BS/R
Stacked 512-MBit DDR-SDRAM
Preliminary Datasheet 2002-09-27 (Rev. 0.92)
Features
CAS Latency and Frequency
CAS Latency
2
2.5
Maximum Operating Frequency (MHz)
DDR266F DDR266A DDR266B DDR200
-7F
-7
-7.5
-8
133
133
125
100
143
143
133
125
• Two 256Mbit DDR-SDRAM packages stacked
with two seperate chip-select (CS) inputs
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
transitions.
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8
µs
Maximum Average Periodic Refresh
Interval
• 2.5V (SSTL_2 compatible) I/O
• V
DDQ
= 2.5V
±
0.2V / V
DD
= 2.5V
±
0.2V
• Stacked two TSOP66 packages
Description
The Stacked 512Mb DDR SDRAM is a high-speed
CMOS, dynamic random-access memory containing
two 256Mbit SDRAM with 268,435,456 bits. It is
internally configured as two quad-bank DRAM.
The two 256Mb DDR SDRAM use a double-data-
rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins. The
upper and lower 256Mbit component can be
selected by two seperated chip-select input signal
CS0 and CS1
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the
DDR SDRAM during Reads and by the memory
controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for
Writes.
The zwo 256Mb DDR SDRAM operate from a differ-
ential clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the posi-
tive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as
well as to both edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of an Active command, which is then
followed by a Read or Write command. The address
bits registered coincident with the Active command
are used to select the bank and row to be accessed.
The address bits registered coincident with the
Read or Write command are used to select the bank
and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read
or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst access.
An auto refresh mode is provided along with a
power-saving power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2.
All outputs are SSTL_2, Class II compatible.
2002-09-27 (0.92)
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