IS61SP25618
256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V +10%, –5% power supply
• 3.3V I/O supply
• Power-down snooze mode
ISSI
®
ADVANCE INFORMATION
MAY 1999
DESCRIPTION
The
ISSI
IS61SP25618 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 262,144
words by 18 bits, fabricated with
ISSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb, conditioned by
BWE
being LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61SP25618 and controlled by the
ADV
(burst
address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frenquency
-166
5
6
166
-150
5
6.7
150
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
Units
ns
ns
MHz
This document contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
SR039-0B
05/14/99
1
IS61SP25618
BLOCK DIAGRAM
ISSI
®
MODE
ADV
CLK
BURST
COUNTER
2
18
ADSC
ADSP
A
A1
A0
CLK2
CLR
256K x 18
MEMORY
ARRAY
16
2
18
ADDRESS
REGISTER
GW
BWE
DQa
BYTE WRITE
REGISTER
18
18
BW1
BW2
DQb
BYTE WRITE
REGISTER
2
CLK
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
CLK2
CLK
CE1
CE2
ENABLE
REGISTER
ENABLE
REGISTER
CE2
OE
DQa - DQb
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
SR039-0B
05/14/99
IS61SP25618
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
ISSI
®
A6
A7
CE
A
VCCQ
B
NC
C
NC
D
DQ9
E
NC
F
VCCQ
G
NC
H
DQ12
J
VCCQ
K
NC
L
DQ14
M
VCCQ
N
DQ16
P
NC
R
NC
T
NC
U
VCCQ
NC
NC
A11
A10
A5
MODE
DQP2
GND
NC
GND
DQ15
GND
NC
GND
DQ13
GND
VCC
NC
NC
GND
DQ11
NC
GND
DQ10
GND
NC
GND
A7
A2
CE2
A3
A6
A4
ADSP
ADSC
VCC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
A16
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
CE
OE
ADV
GW
VCC
CLK
NC
BW2
BW1
GND
GND
GND
GND
A14
NC
BWE
A1
A0
VCC
NC
NC
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8
A9
1
2
3
4
5
6
7
VCC
GND
CLK
CE2
NC
NC
GW
BWE
OE
ADSC
ADSP
ADV
BW2
BW1
CE2
A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
GW
CE
, CE2,
CE2
OE
DQ1-DQ16
MODE
V
CC
GND
V
CCQ
ZZ
GND
Q
DQP1-DQP2
A2-A17
CLK
ADSP
ADSC
ADV
BW1
-
BW2
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
SR039-0B
05/14/99
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Snooze Enable
Isolated Output Buffer Ground
Parity Data I/O DQP1 is parity for DQ1-8;
DQP2 is parity for DQ9-16
3
IS61SP25618
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
ISSI
CE
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
L
X
0
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
®
CE2 ADSP ADSC ADV
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
0
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
Write
2, 4
X
X
X
X
X
X
5
Read
5
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
High-Z
DQ
High-Z
High-Z
High-Z
DQ
High-Z
DQ
High-Z
High-Z
High-Z
NOTES:
1. X = Don't Care. 1 = logic low.
2. Write is defined as either 1) any
BWx
and
BWE
low or 2)
GW
is low.
3.
OE
is an asynchronous signal and is not sampled by the clock CLK.
OE
drives the bus immediately (t
OELZ
) following
OE
going low.
4. On write cycles that follow read cycles,
OE
must be negated prior to the start of the write cycle to ensure proper write data setup
times.
OE
must also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte a
Write Byte b
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
L
BWE
H
L
L
L
L
X
BW1
X
H
L
H
L
X
BW2
X
H
H
L
L
X
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
SR039-0B
05/14/99
IS61SP25618
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CCQ
or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
ISSI
®
LINEAR BURST ADDRESS TABLE (MODE = GND
Q
)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
T
BIAS
T
STG
P
D
I
OUT
V
IN
, V
OUT
V
IN
V
CC
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Voltage on Vcc Supply Relatiive to GND
Value
Unit
–40 to +85
°C
–55 to +150
°C
1.6
W
100
mA
–0.5 to V
CCQ
+ 0.3
V
–0.5 to V
CC
+ 0.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
SR039-0B
05/14/99
5
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