Hardware Design Guide, Revision 8
May 11, 2006
TMXL84622
Ultramapper™
Lite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
1 Introduction
The last issue of this data sheet was April 6, 2006 - Revision 7. A change history is included in
Section 13, Change History,
on page 68.
Red change bars have been installed on all text, figures, and tables that were added or changed. All changes
to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Format-
ting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically
mentioned.
The documentation package for the TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
system chip consists of the following documents:
The Register Description and the System Design Guide. These two documents are available on a password-protected
website.
The
UltramapperLite
Product Description and the
Ultramapper
Lite Hardware Design Guide (this document). These two
documents are available on the public website shown below.
If the reader displays this document using
Acrobat Reader
®
, clicking on any blue text will bring the reader to that reference
point.
To access related documents, including the documents mentioned above, please go to the following public website, or con-
tact your Agere representative (see the last page of this document).
http://www.agere.com/telecom/index.html
This document describes the hardware interfaces of the Agere Systems TMXL84622
UltramapperLite
device. Information
relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams,
ac timing parameters, packaging, and operating conditions are included.
622/155Mbits/s SONET/SDH
ADM Front End
LOPOH
6
DS3/E3/DS2/DS1/E1 PDH
Tributary Termination
High-Speed IF
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
LOPOH
FRM
(X3)
x28/x21
DS1/J1/E1
TPG/TPM
CG
5
PLL IF
CDR
TMUX
Clock/Sync
6
SPEMPR
(x3)
(3-5)
STSPP
S
T
S
X
C
SPEMPR
(x3)
(0-2)
STS-1
LT
System Interfaces
42
Protection Link
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
STS-12/
STM-4/
STS-3/
STM-1
CDR
MRXC
(x3)
x28/x21
VTMPR
3
1
(x6) DS3/E3
(x3) STS-1
(x3) NSMI
(x3) STS-1
(Total of 3 STS-1 Max)
DS1/J1/E1
VT/TU
DS2/E2
DS3/E3
24
180
Low-Speed I/O
Miscellaneous
24
6
(x3)
(x3)
(x3)
E13
M13
MUX
MUX
3
1
Transport Modes
prot.
4
DS1/J1/E1 (x30): x28/x21 +
prot.
4
DS2/E2 (X30): x21/x12 +
prot.
4
VT/TU (X30): x28/x21 +
JTAG
5
JTAG IF
MPU
49
MPU IF
MCDR
6
12
(x3)
(x3) (x3)
DS3/E3 PLL IF
(Optional)
1
1
X3
x28/x21
DS1/E1
x6
DS3/E3
DJA
6
2
TOAC
DS1XCLK,
E1XCLK
6
E2,
DS2,
VC12
VC11
AIS Clocks
DJA
2
POAC
DS3XCLK,
E3XCLK
Power and GND pins not shown
STS-3/STM-1 Mate
Interconnect
10/10/02
Figure 1-1.
UltramapperLite
Block Diagram and High-Level Interface Definition
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Hardware Design Guide, Revision 8
May 11, 2006
Table of Contents
Contents
Page
1 Introduction ........................................................................................................................................................................1
2 Pin Information ...................................................................................................................................................................6
2.1 Ball Diagram ................................................................................................................................................................6
2.2 Package Pin Assignments ...........................................................................................................................................7
2.3 Pin Matrix ...................................................................................................................................................................15
2.4 Pin Types ...................................................................................................................................................................17
2.5 Pin Definitions ............................................................................................................................................................18
3 Operating Conditions and Reliability ................................................................................................................................34
3.1 Absolute Maximum Ratings .......................................................................................................................................34
3.2 Recommended Operating Conditions .......................................................................................................................34
3.3 Handling Precautions ................................................................................................................................................34
3.4 Thermal Parameters (Definitions and Values) ...........................................................................................................35
3.5 Reliability ...................................................................................................................................................................36
3.6 Recommended Powerup Sequence ..........................................................................................................................36
3.7 Power Consumption ..................................................................................................................................................36
4 Electrical Characteristics ..................................................................................................................................................38
4.1 LVCMOS Interface Specifications .............................................................................................................................38
4.2 LVDS Interface Characteristics .................................................................................................................................39
5 Timing ..............................................................................................................................................................................40
5.1 TMUX High-Speed Interface .....................................................................................................................................40
5.2 THSSYNC Characteristics .........................................................................................................................................41
5.3 STS-3/STM-1 Mate Interconnect Timing ...................................................................................................................43
5.4 TOAC, POAC, and LOPOH Timing ...........................................................................................................................44
5.5 DS3/E3/STS-1 Timing ...............................................................................................................................................45
5.6 NSMI Timing ..............................................................................................................................................................46
5.7 Shared Low-Speed Line Timing ................................................................................................................................50
6 Reference Clocks .............................................................................................................................................................51
7 Microprocessor Interface Timing ......................................................................................................................................56
7.1 Synchronous Write Mode ..........................................................................................................................................56
7.2 Synchronous Read Mode ..........................................................................................................................................58
7.3 Asynchronous Write Mode ........................................................................................................................................59
7.4 Asynchronous Read Mode ........................................................................................................................................61
8 Other Timing ....................................................................................................................................................................63
9 Hardware Design File References ...................................................................................................................................63
10 700-Pin PBGAM1T Diagrams .........................................................................................................................................64
11 Device Ordering Information ...........................................................................................................................................66
12 Glossary .........................................................................................................................................................................67
13 Change History ...............................................................................................................................................................68
13.1 Changes to this Document Since Revision 7 ..........................................................................................................68
13.2 Navigating Through an Adobe Acrobat Document ..................................................................................................68
2
Agere Systems Inc.
Hardware Design Guide, Revision 8
May 11, 2006
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Table of Contents
(continued)
Tables
Page
Table 2-1. Package Pin Assignments in Signal Name Order .................................................................................................7
Table 2-2. Package Pin Matrix..............................................................................................................................................15
Table 2-3. Pin Types .............................................................................................................................................................17
Table 2-4. TMUX Block, High-Speed Interface I/O ...............................................................................................................18
Table 2-5. TMUX Block, Protection Link I/O .........................................................................................................................18
Table 2-6. TMUX Block, Clock and Sync I/O ........................................................................................................................19
Table 2-7. STS Cross Connect (STSXC) Block, STS-3/STM-1 Mate Interconnect ..............................................................20
Table 2-8. Synchronous Payload Envelope (SPE) Mapper Block, External PLL Control .....................................................20
Table 2-9. Multirate Cross Connect (MRXC) Block, TOAC Input and Output Channels ......................................................21
Table 2-10. Multirate Cross Connect (MRXC) Block, POAC Input and Output Channels ....................................................21
Table 2-11. DS3/E3/STS-1 Out.............................................................................................................................................22
Table 2-12. DS3/E3/STS-1 In ...............................................................................................................................................22
Table 2-13. NSMI/STS-1 In...................................................................................................................................................23
Table 2-14. NSMI/STS-1 Out................................................................................................................................................24
Table 2-15. Shared Low-Speed Line In ................................................................................................................................24
Table 2-16. Shared Low-Speed Line Out..............................................................................................................................26
Table 2-17. Low-Speed Line In (Negative-Rail in Dual-Rail Mode) ......................................................................................26
Table 2-18. Low-Speed Line Out (Negative-Rail in Dual-Rail Mode)....................................................................................27
Table 2-19. Reference Clocks ..............................................................................................................................................28
Table 2-20. Low-Order Path Overhead Access, Transmit Direction .....................................................................................29
Table 2-21. Low-Order Path Overhead Access, Receive Direction......................................................................................29
Table 2-22. Clock Generator.................................................................................................................................................29
Table 2-23. Microprocessor Interface ...................................................................................................................................30
Table 2-24. Boundary Scan (IEEE
®
1149.1) .........................................................................................................................31
Table 2-25. General-Purpose Interface ................................................................................................................................31
Table 2-26. CDR Interface ....................................................................................................................................................31
Table 2-27. Analog Power and Ground Signals....................................................................................................................32
Table 2-28. Digital Power and Ground Signals.....................................................................................................................33
Table 2-29. No Connects ......................................................................................................................................................33
Table 3-1. Absolute Maximum Ratings .................................................................................................................................34
Table 3-2. Recommended Operating Conditions..................................................................................................................34
Table 3-3. ESD Tolerance.....................................................................................................................................................34
Table 3-4. Thermal Parameter Values ..................................................................................................................................35
Table 3-5. Reliability Data.....................................................................................................................................................36
Table 3-6. Moisture Sensitivity Level ....................................................................................................................................36
Table 3-7. Typical Power Consumption by Application (50 MHz MPU Clock) ......................................................................36
Table 3-8. Typical Power Consumption Per Block................................................................................................................37
Table 4-1. LVCMOS Input Specifications..............................................................................................................................38
Table 4-2. LVCMOS Output Specifications ...........................................................................................................................38
Table 4-3. LVCMOS Bidirectional Specifications ..................................................................................................................38
Table 4-4. LVDS Interface dc Characteristics .......................................................................................................................39
Table 5-1. High-Speed Interface Input Specification.............................................................................................................40
Table 5-2. Protection Link Input Specification.......................................................................................................................40
Table 5-3. High-Speed Interface Outputs .............................................................................................................................41
Table 5-4. Protection Link Outputs .......................................................................................................................................41
Table 5-5. STS-3/STM-1 Mate Interconnect Input Specification...........................................................................................43
Table 5-6. STS-3/STM-1 Mate Interconnect Output Specification ........................................................................................43
Table 5-7. TOAC, POAC, and LOPOH Input Specification...................................................................................................44
Table 5-8. TOAC, POAC, and LOPOH Output Specification ................................................................................................44
Table 5-9. DS3/E3 Input Specification ..................................................................................................................................45
Table 5-10. STS-1 Input Specification ..................................................................................................................................45
Agere Systems Inc.
3
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Hardware Design Guide, Revision 8
May 11, 2006
Table of Contents
(continued)
Tables
Page
Table 5-11. DS3/E3/STS-1 Output Specification ..................................................................................................................45
Table 5-12. NSMI Input Specifications..................................................................................................................................49
Table 5-13. NSMI Output Specifications ...............................................................................................................................49
Table 5-14. Shared Low-Speed Line Timing Input Specification ..........................................................................................50
Table 5-15. Shared Low-Speed Line Timing Output Specification........................................................................................50
Table 6-1. High-Speed Interface Input Clocks Specifications ...............................................................................................51
Table 6-2. Protection Link Input Clock Specifications ...........................................................................................................51
Table 6-3. DS3/E3/STS-1 Input Clocks Specifications .........................................................................................................51
Table 6-4. DS1/E1 DJA Input Clocks Specifications.............................................................................................................51
Table 6-5. M13/E13 Input Clocks Specifications...................................................................................................................52
Table 6-6. DS3/E3 DJA Input Clocks Specifications.............................................................................................................52
Table 6-7. LOPOH Input Clock Specifications ......................................................................................................................52
Table 6-8. Microprocessor Interface Input Clocks Specifications .........................................................................................52
Table 6-9. PLL Input Clock Specifications ...........................................................................................................................52
Table 6-10. High-Speed Interface Output Clocks Specifications ..........................................................................................52
Table 6-11. Protection Link Output Clocks Specifications.....................................................................................................52
Table 6-12. Line Timing Interface Output Clocks Specifications...........................................................................................53
Table 6-13. TOAC Output Clocks Specifications ..................................................................................................................53
Table 6-14. POAC Output Clocks Specifications ..................................................................................................................53
Table 6-15. DS3/E3/STS-1 Output Clocks Specifications.....................................................................................................54
Table 6-16. LOPOH Output Clock Specifications .................................................................................................................54
Table 6-17. NSMI Output Clocks Specifications ...................................................................................................................54
Table 6-18. PLL Output Clocks Specifications......................................................................................................................54
Table 6-19. Shared Low-Speed Receive Line Input/Output Clocks Specifications...............................................................54
Table 6-20. Shared Low-Speed Transmit Line Input/Output Clocks Specifications..............................................................55
Table 6-21. NSMI Input/Output Clocks Specifications ..........................................................................................................55
Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications.....................................................................57
Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications.....................................................................58
Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ...................................................................60
Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications...................................................................62
Table 8-1. General-Purpose Inputs.......................................................................................................................................63
Table 8-2. Miscellaneous Output ..........................................................................................................................................63
Table 8-3. General-Purpose Output......................................................................................................................................63
Table 11-1. Device Ordering Information ..............................................................................................................................66
4
Agere Systems Inc.
Hardware Design Guide, Revision 8
May 11, 2006
TMXL84622
UltramapperLite
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Table of Contents
(continued)
Figures
Page
Figure 1-1. UltramapperLite Block Diagram and High-Level Interface Definition ...................................................................1
Figure 2-1. UltramapperLite Package Diagram (Top View)....................................................................................................6
Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................40
Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................40
Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................41
Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................41
Figure 5-5. THSSYNC Timing Diagram for Synchronized VTs ............................................................................................42
Figure 5-6. Relationship Between THSSYNC and THSD ....................................................................................................42
Figure 5-7. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................43
Figure 5-8. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................43
Figure 5-9. TOAC, POAC Timing .........................................................................................................................................44
Figure 5-10. LOPOH Timing.................................................................................................................................................44
Figure 5-11. DS3/E3 Interface Diagram in M13/E13 Block ..................................................................................................45
Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode ..........................................................................................46
Figure 5-13. NSMI Clock and Data Diagram for SPEMPR NSMI Mode...............................................................................46
Figure 5-14. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O).....................47
Figure 5-15. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O)......................47
Figure 5-16. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) .............48
Figure 5-17. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .......................................................................49
Figure 5-18. Shared Low-Speed Line Clock and Data Timing .............................................................................................50
Figure 7-1. Microprocessor Interface Synchronous Write Cycle—(MPMODE Pin = 1)........................................................56
Figure 7-2. Microprocessor Interface Synchronous Read Cycle—(MPMODE Pin = 1)........................................................58
Figure 7-3. Microprocessor Interface Asynchronous Write Cycle—(MPMODE Pin = 0) ......................................................59
Figure 7-4. Microprocessor Interface Asynchronous Read Cycle—(MPMODE Pin = 0)......................................................61
Figure 10-1. 700-Pin PBGAM1T Physical Dimension ..........................................................................................................64
Figure 10-2. Bottom View of 700-Pin PBGAM1T Balls Location ..........................................................................................65
Agere Systems Inc.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
