CY7C1328F
4-Mb (256K x 18) Pipelined DCD Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 256K × 18-bit common I/O architecture
• 3.3V –5% and +10% core power supply (V
DD
)
• 3.3V / 2.5V I/O supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1328F operates from a +3.3V core power supply
while all outputs operate with a +3.3V or a +2.5V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
325
40
225 MHz
2.6
290
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
100 MHz
4.5
205
40
Unit
ns
mA
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05220 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 19, 2004
CY7C1328F
Functional Block Diagram—256Kx18
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQ
s,
DQP
A
DQP
B
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document #: 38-05220 Rev. *A
Page 2 of 17
CY7C1328F
Pin Configurations
100-pin TQFP
Top View
BYTE B
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
CY7C1328F
(256K x 18)
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
BYTE A
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
Document #: 38-05220 Rev. *A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 17
CY7C1328F
Pin Descriptions
Pin
A0, A
1
, A
TQFP
37,36,32,33
34,35,44,45,
46,47,48,49,
50,80,81,82,
99,100
93,94
88
Type
Description
Input-
Address Inputs used to select one of the 256K address locations.
Sampled at
Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
are fed to the two-bit counter.
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[A:B]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
BW
A ,
BW
B
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
87
89
98
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE
1
and CE
2
to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW.
When
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous
LOW.
When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous
LOW.
When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal opera-
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP
[A:B]
are
placed in a three-state condition.
Ground
I/O Power
Supply
I/O Ground
Input-
Static
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied
to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
Page 4 of 17
97
92
86
ADV
ADSP
83
84
ADSC
85
ZZ
64
DQs
DQP
[A:B]
58,59,62,63
68,69,72,73,
74,8,9,
12,13
18,19,22,23,
24
17,40,67,90
4,11,20,27,
54,61,70,77
5,10,21,26,
55,60,71,76
31
V
DD
V
SS
V
DDQ
V
SSQ
MODE
15,41,65,91 Power Supply
Power supply inputs to the core of the device.
Document #: 38-05220 Rev. *A
CY7C1328F
Pin Descriptions
(continued)
Pin
NC
TQFP
1,2,3,6,7,14,
16,25,28,29,
30,38,39,42,
43,51,52,53,
56,57,66,75,
78,79,95,96
Type
Description
No Connects.
Not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1328F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:B]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE
1
, CE
2
, CE
3
and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
co
if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
The CY7C1328F is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will three-state immediately
after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW
[A:B]
) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW
[A:B]
signals. The CY7C1328F provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1328F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BW
[A:B]
) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ
X
is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1328F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
X
inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ
X
are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Document #: 38-05220 Rev. *A
Page 5 of 17
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