Data Sheet
PT7C4781
PLL Multi-Clock Generator
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Features
•
•
•
•
•
3.3V operation
Low Jitter (Typ. 200ps). High accuracy outputs
12MHz master clock inout
3 kinds clock output: 27MHz, 24.576MHz and
12.288MHz
SOIC-8 package
The PT7C4781 is low cost, multi-clock generator Phase
Lock Loop (PLL).
The PT7C4781 can generate three clocks from a 12MHz
reference input frequency.
The device gives customers both cost and space
savings by eliminating external components and enables
customers to achieve the very low jitter performance
needed for high performance audio digital-to-analog
converters (DAC) and/or analog-to-digital converters
Package
Lead free SOIC-8
(ADC).
The
PT7C4781
is
ideal
for
MPEG-2
Ordering Information
Part No.
PT7C4781WE
applications which use a 27MHz master clock such as
DVD players, DVD add-on cards for multimedia PCs,
digital HDTV systems, and set-top boxes.
Description
Block Diagram
OE
XT1
OSC
XT2
Counter N
Counter M
Phase Detector
and
Loop Filter
VCO
OUT3:
27MHz
Output
Buffer
Counter N
Counter M
Phase Detector
and
Loop Filter
VCO
1/2
Divider
OUT1:
24.576MHz
OUT2:
12.288MHz
PT0170(12/06)
1
Ver:1
Data Sheet
PT7C4781
PLL Multi-Clock Generator
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Pin Configuration
CLK3
GND
XTI
XTO
1
2
3
4
SOIC-8
8
7
6
5
OE
VDD
CLK1
CLK2
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
CLK3
GND
XTI
XTO
CLK2
CLK1
VDD
OE
Type
O
P
I
O
O
O
P
I
27MHz clock output.
Ground.
12-MHz crystal oscillator, or external clock input
12-MHz crystal oscillator, must be OPEN for external clock input mode
12.288MHz clock output.
24.576MHz clock output.
+3.3V power supply.
Clock output enable with internal pull-up resistor. When OE is high level, CLK1, CLK2, CLK3
output relative clocks. When OE is low, they are in three-state output.
Description
PT0170(12/06)
2
Ver:1
Data Sheet
PT7C4781
PLL Multi-Clock Generator
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Function description
Master Clock
The PT7C4781 consists of a dual PLL clock and master clock generator which generates three system clocks from a 12MHz
master clock. The PLL is designed to accept a 12MHz master clock or crystal oscillator.
The master clock can be either a crystal oscillator placed between XTI and XTO, or an external input to XTI. If an external master
clock is used, XTO should be left open.
System Clock Output
CLK1, CLK2, CLK3 output frequency and phase relation is shown blow.
Pin
CLK1
CLK2
CLK3
Function control
All 3 outputs can be controlled by OE pin. When OE pin is set to GND, internal oscillation is shut off and all 3 outputs enter into
three-state output. OE pin is internally pulled up by about 50kW resistor. So if no connection to OE, CLK1 outputs 24.576MHz;
CLK2 outputs 12.288MHz; CLK3 outputs 27MHz.
Output frequency (MHz)
24.576
12.288
27
CLK1:24.576MHz
CLK2:12.288MHz
Phase relation
No relation to CLK1 and CLK2
Maximum Ratings
Storage Temperature......................................................................................-55oC to +150oC
Ambient Operating Temperature..................................................................-40oC to +85oC
Supply Voltage to Ground Potential (V
CC
)..................................................-0.3V to + 6.5V
Supply Voltage Differences............................................................................................±0.1V
GND Voltage Differences...............................................................................................±0.1V
Digital Input Voltage ..............................................................................-0.3V to Vcc+0.3V
Digital Output Voltage ...........................................................................-0.3V to Vcc+0.3V
Input Current(Any pins except supplies)
..........................................±
10mA
Power Dissipation.............................................................................................................500mW
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC Electrical Characteristics
All specifications at T
A
= -10~+85°C, V
DD
= +3.3V, 12MHz crystal, unless otherwise noted.
Description
Test Conditions
Min
Power Supply Requirement
Voltage range: V
DD
, V
DDP
3.0
Supply current: I
DDS
OE: GND
V
DD
= 3.3V, Crystal
12MHz, no load
I
DD
OE: VDD
Input/Output
Input threshold: V
IH
OE, XTI pins
0.7V
DD
V
IL
OE, XTI pins
Internal pull-up resistor: r
OE pin
100
Output driving: I
OH
V
OH
= V
DD
-0.5, V
DD
= 3.3V
6
I
OL
V
OL
= 0.5, V
DD
= 3.3V
6
Output leakage current: I
OZ
Three-state outputs
Typ
3.3
20
22
Max
3.6
40
25
Unit
V
µA
mA
V
V
kΩ
mA
mA
µA
167
8
8
0.3V
DD
200
10
PT0170(12/06)
3
Ver:1
Data Sheet
PT7C4781
PLL Multi-Clock Generator
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AC Electrical Characteristics
All specifications at T
A
= -10~+85°C, V
DD
= +3.3V, 12MHz crystal, unless otherwise noted.
Description
Test Conditions
Min
CLK1 pin
Output frequency:
t
1
CLK2 pin
CLK3 pin
Output duty cycle:
t
2
45
Rising edge slew rate:
t
3
0.75
Falling edge slew rate:
t
4
0.75
Time for output to enter three-state mode
Output three-state timing: t
5
Time for output to leave three-state mode
Clock jitter:
t
6
Peak-to-peak period jitter, CLK outputs measured at V
DD
/2
Lock time:
1)
t
7
PLL lock time from power-up
Note:
1) only reference for design.
Typ
24.576
12.288
27
50
Max
Unit
MHz
55
400
300
200
1
3
%
V/ns
V/ns
µs
ns
ps
ms
Fig 1. PT7C4781 duty cycle and slew rate
t
2
Output
t
1
t
3
t
4
Fig 2. PT7C4781 output three-state timing
OE
All three
state outputs
t
5
t
5
Fig 3. PT7C4781 CLK output jitter
t
6
CLK
Output
PT0170(12/06)
4
Ver:1
Data Sheet
PT7C4781
PLL Multi-Clock Generator
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Application Circuit
PT7C4781
27MHz output
1
2
3
12MHz
C1
4
C2
XTO
CLK3
GND
XTI
OE
VDD
CLK1
CLK2
8
7
6
5
24.576MHz output
12.288MHz output
C
+3.3V
Note:
C adopts 0.1uF ceramic and 10uF tantalum capacitor typical, depending on quality of power supply and pattern layout.
Crystal Loading Capacity (CL)
14p
18p
C1
22p
30p
C2
22p
30p
* C1=C2=CL x 2 - 6p
Mechanical Information
WE (SOIC-8)
8
.149 3.78
.157 3.99
.0099 0.25
x 45
o
.0196 0.50
0-8
o
0.40 .016
1.27 .050
.2284
.2440
5.80
6.20
.0075 0.19
.0098 0.25
1
.189 4.80
.196 5.00
.016
.026
0.406
0.660
REF
.050
BSC
1.27
.053 1.35
.068 1.75
SEATING PLANE
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012 AA
PT0170(12/06)
5
Ver:1
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