TSS4550
IrDA
®
– UART Integrated Interface
Description
The TSS4550 is a very low power consumption
integrated circuit. It combines the functions of a
PC–compatible UART and an IrDA interface circuit. It
provides both serial and infrared communication
interface ports to a processor. It connects to an external
bus which may be either multiplexed address/data bus or
separate address and data buses. It incorporates a
FIFO–buffered high speed UART. The output of the
UART may be connected, using a 3 way multiplexer, to
either an external IrDA transceiver via an internal pulse
shaping circuit or directly to one of two separate
MODEM compatible output ports (logic levels). The
pulse shaper is compliant to the IrDA standards
revision 1.2.
The TSS4550 also provides additional peripheral
support by way of control outputs and a parallel I/O port.
In addition to normal operating modes, the device has a
power–down mode for power saving and test modes to
assist with board manufacturing.
Features
D
General purpose processor interface with separate
address and data buses
D
Intel compatible ALE input for multiplexed
address/data bus
D
UART with 2x16 bytes receive and transmit FIFO
D
Programmable rate from 50 to 115200 bauds
D
Pulse shaping circuit for direct connection to IrDA
transceivers
D
2 MODEM compatible ports (DTR, RTS, Sout, DSR,
DCD, CTS, Sin)
D
6 MODEM inputs may be used as general–purpose
interrupts
D
2 general–purpose control outputs
D
6 bits parallel I/O interface
D
Global interrupt request output
D
On–chip oscillator using a low–cost 32 kHz crystal
D
Buffered clock output for real–time clock reference
D
Low noise integrated PLL
D
Wide operating voltage range: 2.7V to 5.5V
D
Very low operating power consumption: 3 mW at 3V
D
Power–down mode
D
Industrial and Commercial temperature ranges
D
TQFP64 (1.5 mm thickness) and PLCC68
D
Test modes for automated test on board
Applications
D
Telecommunication
MODEM, PABX...)
D
Portable Equipments
D
Medical & Industrial data collection
Products
(mobile
phones,
D
Internet TV Boxes, Video Conferencing Systems
D
Intelligent Remote Control
D
Electronic Money Terminals
Rev. D – September 11, 1998
Preliminary
1
TSS4550
Block Diagram
D(7:0)
Bi–directional
FIFO
UART
IrDA 1.2
Pulse shaping
A(3:0), control
Interrupt
Reset
CLKout
Reset
clock PLL
Interface
controller
1:3
Multiplexer
IrDA Transceiver
MODEM Serial 1
MODEM Serial 2
External control
Parallel I/O
32.768kHz
Figure 1. Block Diagram of TSS4550.
Pin Description
Function
Data bus
Address bus
Bus interface control
Pins
D[7:0]
A[3:0]
ALE
RD
RD
WR
WR
CS
CS
RESET
INT
Type
I/O
strong
I
I
I
I
I
I
I
I
I
O
medium
I
O
O
I
O
medium
O
O
medium
Rest
State
I / low
I / low
I / low
I / low
I / high
I / low
I / high
I / low
I / high
I / high
O / low
–
–
O / low
I / high
O / low
O / low
O / high
Data bus
Address bus
Description
Address Latch Enable, address latched on falling edge
Read strobe active high (must be tied low when not used)
Read strobe active low (must be tied high when not used)
Write strobe active high (must be tied low when not used)
Write strobe active low (must be tied high when not used)
Chip select active high (must be tied low when not used)
Chip select active low (must be tied high when not used)
Hardware reset, active low
Interrupt to external bus, active high
External crystal input
External crystal output
Buffered clock
From external IrDA transceiver – received data (inverted)
To external IrDA transceiver – transmitted data
External IrDA transceiver shutdown (when low) or general–purpose output,
active high
MODEM 1 Request To Send or general–purpose output, active low
Clocks
XTAL1
XTAL2
CLKOUT
IrDA Interface
IRRX
TXIR
IRSD
MODEM Serial 1
RTS1
2
Preliminary
Rev. D – September 11, 1998
TSS4550
Function
Pins
DTR1
SOUT1
DSR1
DCD1
CTS1
SIN1
MODEM Serial 2
RTS2
DTR2
SOUT2
DSR2
DCD2
CTS2
SIN2
External control
SEL1
SEL2
Parallel I/O
Parallel I/O
Miscellaneous
P[2:0]
P[5:3]
TEST
XPLLF
Oscillator Power
VCCO
VSSO
PLL Power
XVCC
XVEE
PLL HF Power
XVCCHF
XVEEHF
Core Power
VCCA
VSSA
Buffers Power
VCCB
VSSB
Type
O
medium
O
medium
I
I
I
I
O
medium
O
medium
O
medium
I
I
I
I
O
medium
O
I/O
strong
I/O
strong
I
PLL
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
GND
Rest
State
O / high
O / high
I / high
I / high
I / high
I / high
O / high
O / high
O / high
I / high
I / high
I / high
I / high
O / low
Description
MODEM 1 Data Terminal Ready or general–purpose output, active low
MODEM 1 Serial data transmit
MODEM 1 Data Set Ready or interrupt input, active low
MODEM 1 Data Carrier Detect or interrupt input, active low
MODEM 1 Clear To Send or interrupt input, active low
MODEM 1 Serial data receive
MODEM 2 Request To Send or general–purpose output, active low
MODEM 2 Data Terminal Ready or general–purpose output, active low
MODEM 2 Serial data transmit
MODEM 2 Data Set Ready or interrupt input, active low
MODEM 2 Data Carrier Detect or interrupt input, active low
MODEM 2 Clear To Send or interrupt input, active low
MODEM 2 Serial data receive
Select or general–purpose output, active high
I / low
O / low
I / high
–
–
–
–
–
–
–
–
–
–
–
Parallel I/O port
Parallel I/O port
Test mode enable, internally pulled–up, active low
PLL Filter pin
VCC supply for on–chip oscillator
GND pin for on–chip oscillator
VCC supply for PLL
GND pin for PLL
VCC supply for PLL HF
GND pin for PLL HF
VCC supply for core
GND pin for core
VCC supply for I/O buffers ring
GND pin for I/O buffers ring
Table 1. TSS4550 Pin Description by Groups
Rev. D – September 11, 1998
Preliminary
3
TSS4550
Functional Description
Figure 1. highlights the different functions included in TSS4550, which are further detailed in this section.
Figure 2. provides a more detailed view highlighting how the registers are mapped to functions. The register names
are given besides each block, along with their read/write capability (R/W). They are further detailed in the
Programming Interface section.
ALE
RD, RD
WR, WR
CS, CS
A[3:0]
D[7:0]
8–bit Buffer
1.8432
TXIR
Transmit
Shift
Register
DLM, DLL (R/W)
Baud Rate
Divisor Latch
S
IRRX
3.6864
Clock
and
Reset
Receive
FIFO
FDR (R)
Programmable
16–bit Counter
8–bit Buffer
Receive
Shift
S
Register
3 to 1
SIN1
SIN2
1 to 3
SOUT1
SOUT2
Transmit
Bus
Interface
FDR (W)
FIFO
XTAL1
XTAL2
XPLLF
CLKOUT
RESET
RTS1
DTR1
RTS2
DTR2
MODEM
Control
CTS1
DSR1
DCD1
CTS2
DSR2
DCD2
RBR (R)
Line Status
LCR (R/W)
LSR (R/W)
⊕
General
PIODR (R/W)
PIODDR (R/W)
Purpose
I/O
MCR (R/W)
MSR (R/W)
P[2:0]
P[5:3]
IRSD
SEL1
SEL2
TEST
INT
S
Interface
Controller
IER (R/W) SR (R)
IIR (R)
IMMR (R)
ISR (R)
CR1 (R/W)
CR2 (W)
Figure 2. Detailed Block Diagram of TSS4550.
Transmit and Receive FIFO
The transmit and receive FIFO (see Figure 1. ) are used to buffer the data between the UART and the external 8 bits
data bus. These FIFO are 16 bytes deep in both directions, 8 bits wide in transmit (external bus to UART) and 10 bits
wide in receive (UART to external bus). The wider receive path is used to convey the framing error and parity error
information made available by the UART with each received byte. The received byte status bits are read from the FIFO
using the status register (SR), see the Interface Controller section below.
UART / MODEM
The UART (see Figure 1. ) is a high speed unit capable of operating at serial line speeds up to 115,200 bits/second from
an internal clock input of 3.6864MHz. It supports the following signal lines: DTR, RTS, Serial output, DSR, DCD,
4
Preliminary
Rev. D – September 11, 1998
TSS4550
CTS and Serial input. Main UART operations are controlled and monitored by internal UART registers which are
available at the external bus interface. Line status is made available with each received data byte and stored in the
associated extra receive FIFO bits. Data transfers between the UART and FIFO are controlled by the Interface
Controller block.
There is no automatic flow control, so DTR, RTS, DSR, DCD and CTS should be managed by software as required.
If MODEM lines are not implemented, they can be used as general–purpose outputs or interrupt inputs.
There is no dedicated Ring Indicator input.
Multiplexer
The 1 to 3 multiplexer (see Figure 1. ) is used to route the UART serial input/output and MODEM input signals to and
from one of three ports: the IrDA 1.0 interface and two MODEM serial interfaces. The multiplexer is controlled by
two bits in the Interrupt Mask and Misc. Register (IMMR).
Only the UART serial data and input signals are multiplexed. These are the Serial output, Serial input, DCD, CTS and
DSR signals. The RTS and DTR signals for the two MODEM ports can be produced independently by software for each
port using the MODEM Control Register (MCR).
IrDA 1.0 Pulse Shaping
TSS4550 may directly drive an external IrDA 1.0 transceiver through an internal pulse shaping circuit. The function
is that of transmit pulse narrowing and receive pulse stretching. This unit generates transmit pulse widths of 1.6
µs
nominal pulse width (3/16
ths
bit time of the maximum bit rate of 115,200 bits/second). At all times, the pulse shaper
transmit output is kept in a state such that the transmit LED is normally off only being energized for the minimum
on–times during data transmission. The pulse shaping circuit is reset by the PSRST bit in the Control Register 1 (CR1)
or by the global hardware reset (RESET).
Interface Controller
The interface controller (see Figure 2. ) provides control and monitoring of the data transfers between the external bus
and FIFO and the UART and FIFO. It also allows the UART to be directly accessed by the external bus for UART control
and monitoring. Additional miscellaneous control functions are provided for features such as enabling of external
devices and parallel I/O.
It generates an external bus interrupt on the following conditions:
D
Detection of an UART interrupt: changes in DSR, DCD or CTS, received characters with errors, break...
D
Detection of receive FIFO becoming half–full.
D
Detection of receive FIFO non–empty for longer than 3 character length times with no more characters being
received.
D
Detection of transmit FIFO becoming half–empty.
D
Detection of toggling inputs on MODEM port 1 when not selected
D
Detection of toggling inputs on MODEM port 2 when not selected
The received serial data from the UART is written into the receive FIFO and made available to the external bus via
the FIFO Data Register (FDR – which is the output of the receive FIFO). The framing error and parity error bits
(available from the UART along with each received byte) are also stored in the receive FIFO. These status bits are made
available to the external bus in the Status Register (SR). When framing error or parity error information is needed, SR
must be read before FDR is read. When FDR is read, the next data byte and associated status bits are popped off the
FIFO so the SR locations are overwritten by the new status bits at the same time the data is available in FDR. If the
status bits for a data byte are not read before reading another data byte, the status bits for the first byte will be overwritten
with the status bits for the newly read data byte.
The receive FIFO will not be affected by external system reads whilst empty. An external read in these circumstances
will not change FDR and SR contents. The receive FIFO will also not accept any more data from the UART when full.
Rev. D – September 11, 1998
Preliminary
5
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