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ordering part number with the prefix “CY”.
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to
www.cypress.com.
MB9B120M Series
32-bit Arm
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B120M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the Arm
®
Cortex
®
-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I
2
C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in FM3 Family Peripheral Manual.
Features
32-bit Arm
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission/reception by CTS/RTS (only ch.4)
24-bit System timer (Sys Tick): System timer for OS task
management
Various error detection functions available (parity errors,
On-chip Memories
[Flash memory]
Dual operation Flash memory
Dual
framing errors, and overrun errors)
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit
length)
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
LIN break delimiter generation (can be changed to 1 to 4-bit
length)
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max eight channels)
4 channels with 16 stepsx9-bit FIFO (ch.0/1/3/4), 4 channels
without FIFO (ch.2/5/6/7)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[I
2
C]
Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps)
supported
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
Cypress Semiconductor Corporation
Document Number: 002-05655 Rev. *D
• 198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February
9,
2018
MB9B120M Series
DMA Controller (Eight channels)
The DMA controller has an independent bus from the CPU, so
the CPU and the DMA controller can process simultaneously.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in port relocate function
Up to 65 high-speed general-purpose I/O ports @ 80 pin
package
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 26 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 0.8 μs @ 5V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Some ports are 5V tolerant.
See "List of Pin Functions" and "I/O Circuit Type" to confirm
the corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The dual timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Quadrature Position/Revolution Counter (QPRC)
(Max two channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
D/A Converter (Max two channels)
R-2R type
10-bit resolution
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-05655 Rev. *D
Page 2 of 101
MB9B120M Series
Multi-Function Timer
The multi-function timer is composed of the following blocks.
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a “Hardware”
watchdog and a “Software” watchdog.
The “Hardware” watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the “Hardware” watchdog
is active in any low-power consumption modes except RTC,
Stop, Deep Standby RTC, Deep Standby Stop modes.
16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
Output compare × 6ch./unit
A/D activation compare × 2ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
The following functions can be used to achieve motor control.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D converter activate function
DTIF (motor emergency stop) interrupt function
Real-Time Clock (RTC)
The real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillator, and Main PLL).
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The watch counter is used for wake up from the Sleep and
Timer mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 23 external interrupt input pins @ 80 pin Package
Include one non-maskable interrupt (NMI) input pin
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset is
asserted.
Document Number: 002-05655 Rev. *D
Page 3 of 101
MB9B120M Series
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41-bit) is set.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes are supported.
Power Supply
Wide range voltage:
VCC = 2.7 V to 5.5 V
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value
of RAM and not)
Deep Standby Stop (selectable between keeping the value
of RAM and not)
Document Number: 002-05655 Rev. *D
Page 4 of 101
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