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L-ET901-L-DB: 产品描述Ethernet Transceiver, PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48; 产品类别无线/射频/通信电信电路; 文件大小346KB，共26页; 制造商Broadcom(博通)

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L-ET901-L-DB概述

Ethernet Transceiver, PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48

L-ET901-L-DB规格参数

参数名称	属性值
包装说明	LFQFP,
Reach Compliance Code	compliant
JESD-30 代码	S-PQFP-G48
JESD-609代码	e6
长度	7 mm
功能数量	1
端子数量	48
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	1.6 mm
标称供电电压	3.3 V
表面贴装	YES
电信集成电路类型	ETHERNET TRANSCEIVER
温度等级	COMMERCIAL
端子面层	TIN BISMUTH
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
宽度	7 mm
Base Number Matches	1

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Data Sheet

May 9, 2006

ET901 Fast Ethernet Transceiver

Features

■

Overview

The ET901 series are physical layer devices for

Ethernet 10Base-T and 100Base-TX using category

five unshielded and type 1 shielded cable. This VLSI

device is designed for easy implementation of

10/100 Mbits/s fast Ethernet LANs. It interfaces to a

MAC (either a single chip or integrated in south-

bridge/CPU/switch) through an MII interface ensuring

interoperability between products from different ven-

dors.

Single-chip 10Base-T/100Base-TX transceiver.

Dual speed: 10/100 Mbits/s.

Half-/full-duplex operation.

Media-independent interface (MII) to

IEEE 802.3

MAC.

MDC/MDIO interface for configuration and status.

Autonegotiation support.

48-pin LQFP package.

■

Serial

EEPROM

LEDs

Host

Interface

IEEE 802.3

MAC

ET901

MII

Interface

PHY

TX±

RX±

Media-

Dependent

Interface

(MDI)

Boot

ROM

(Optional)

Figure 1. Typical System Block Diagram

Agere Systems - Proprietary

ET901 Fast Ethernet Transceiver

Data Sheet

May 9, 2006

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1

Overview.................................................................................................................................................................... 1

Functional Description ............................................................................................................................................... 4

General ..................................................................................................................................................................4

Status Information ..................................................................................................................................................4

Pin Strapping .......................................................................................................................................................10

Register Overview ................................................................................................................................................11

Register Bit Summary ..........................................................................................................................................12

Absolute Maximum Ratings .................................................................................................................................17

dc Characteristics ................................................................................................................................................17

ac Characteristics ................................................................................................................................................18

Package Mechanical Specifications ........................................................................................................................25

Lead-Free Package Infrared Reflow........................................................................................................................26

Ordering Information................................................................................................................................................26

Figure

Page

Figure 1. Typical System Block Diagram ........................................................................................................................... 1

Figure 2. Internal Block Diagram ....................................................................................................................................... 5

Figure 3. 48-Pin LQFP Package (Top View) ..................................................................................................................... 6

Figure 4. Power Reset Timing ......................................................................................................................................... 17

Figure 5. MI Interface MDIO Timing ................................................................................................................................ 19

Figure 6. LED On/Off Timing ........................................................................................................................................... 20

Figure 7. MII Transmit Data Timing ................................................................................................................................. 20

Figure 8. MII Receive Data Timing .................................................................................................................................. 20

Figure 9. MII Heartbeat Timing ........................................................................................................................................ 21

Figure 10. MII Jabber Timing ........................................................................................................................................... 21

Figure 11. MII Normal Link Pulse Timing ......................................................................................................................... 21

Figure 12. MII Autonegotiation Fast Link Pulse Timing ................................................................................................... 22

Figure 13. 100 Mbits/s Receive Packet Timing ............................................................................................................... 22

Figure 14. 100 Mbits/s Transmit Packet Timing .............................................................................................................. 23

Figure 15. 10 Mbits/s Receive Packet Timing ................................................................................................................. 23

Figure 16. 10 Mbits/s Transmit Packet Timing ................................................................................................................ 24

Figure 17. ET901 LQFP-48 Package (7 mm × 7 mm) ..................................................................................................... 25

Table

Page

Table 1. LED Output Pin List (Alphabetical Order) ............................................................................................................ 4

Table 2. Pin List (Alphabetical Order) ................................................................................................................................ 7

Table 3. Media-Independent Interface (MII) ...................................................................................................................... 8

Table 4. Management Interface (MI) ................................................................................................................................. 9

Table 5. LED Outputs ........................................................................................................................................................ 9

Table 6. Physical Cable Connection .................................................................................................................................. 9

Table 7. Resets, Clocks, Control, and Status ................................................................................................................. 10

Table 8. Power and Ground ............................................................................................................................................ 10

Table 9. Strap Options .................................................................................................................................................... 10

Table 10. Register Summary ........................................................................................................................................... 11

Table 11. Registers Defined by

IEEE 802.3u

Standard ................................................................................................... 12

Table 12. Vendor-Defined Registers ............................................................................................................................... 13

Table 13. Offset 0 (00H)—MI Control (3100H)RW .......................................................................................................... 13

Table 14. Offset 1 (01H)—MI Status (7849H) RO ........................................................................................................... 14

Table 15. Offset 2 (02H)—PHY Identifier 0 (0101H) RO ................................................................................................. 14

Table 16. Offset 3 (03H)—PHY Identifier 1 (8F20H)RO .................................................................................................. 14

Table 17. Offset 4 (04H)—Autonegotiation Advertisement Base Page (05E1H) RW ...................................................... 14

Agere Systems - Proprietary

Data Sheet

May 9, 2006

ET901 Fast Ethernet Transceiver

Table of Contents

(continued)

Table

Page

Table 18. Offset 5 (05H)—Link Partner Advertisement Base Page (0000H) RO ............................................................15

Table 19. Offset 6 (06H)—Autonegotiation Expansion (0004H) RO ...............................................................................15

Table 20. Offset 7 (07H)—Autonegotiation Advertisement Next Page (2001H) RW .......................................................15

Table 21. Offset 8 (08H)—Link Partner Advertisement Next Page (0000H) RO .............................................................15

Table 22. Offset 16 (10H)—PHY Configuration 1 (0800H) RW .......................................................................................16

Table 23. Offset 20 (14H)—PHY Status (0000H) RO ......................................................................................................16

Table 24. Absolute Maximum Ratings .............................................................................................................................17

Table 25. dc Characteristics ............................................................................................................................................17

Table 26. 100Base-T Transmitter Characteristics ...........................................................................................................18

Table 27. 10Base-T Transmitter Characteristics .............................................................................................................18

Table 28. Crystal Oscillator Characteristics .....................................................................................................................18

Table 29. PLL Frequency Multiplier Characteristics ........................................................................................................19

Table 30. Transformer Characteristics ............................................................................................................................19

Table 31. MI Interface MDIO Output Timing ....................................................................................................................19

Table 32. LED On/Off Timing ..........................................................................................................................................20

Table 33. MII Transmit Data Timing ................................................................................................................................20

Table 34. MII Receive Data Timing .................................................................................................................................20

Table 35. MII Heartbeat Timing .......................................................................................................................................21

Table 36. MII Jabber Timing ............................................................................................................................................21

Table 37. MII 10Base-T Normal Link Pulse Timing .........................................................................................................21

Table 38. MII Autonegotiation Fast Link Pulse Timing ....................................................................................................22

Table 39. 100 Mbits/s Receive Packet Timing .................................................................................................................22

Table 40. 100 Mbits/s Transmit Packet Timing ...............................................................................................................23

Table 41. 10 Mbits/s Receive Packet Timing ..................................................................................................................23

Table 42. 10 Mbits/s Transmit Packet Timing .................................................................................................................24

Agere Systems - Proprietary

ET901 Fast Ethernet Transceiver

Data Sheet

May 9, 2006

Functional Description

General

The

ET901

is a complete 10/100 Mbits/s ethernet media interface IC. The

ET901

has the following main sections:

controller interface, encoder, decoder, scrambler, descrambler, clock and data recovery, twisted pair transmitter,

twisted pair receiver, and MI serial port. A block diagram is shown in

Figure 2.

The

ET901

can operate as a 100Base-TX device (hereafter referred to as 100 Mbits/s mode) or as a 10Base-T

device (hereafter referred to as 10 Mbits/s mode). The differences between 100 Mbits/s mode and 10 Mbits/s mode

are data rate, signaling protocol, and allowed wiring. 100 Mbits/s TX mode uses two pairs of category 5 or better

UTP or STP twisted-pair cable with 4B5B encoded, scrambled, and MLT-3 coded 62.5 MHz ternary data to achieve

a throughput of 100 Mbits/s. 10 Mbits/s mode uses two pairs of category 3 or better UTP or STP twisted-pair cable

with Manchester-encoded, 10 MHz binary data to achieve a 10 Mbits/s. The data symbol format on the twisted-pair

cable for the 100 Mbits/s and 10 Mbits/s modes is defined in the

IEEE 802.3

specification.

On the transmit side for 100 Mbits/s TX operation, data is received on the controller interface from an external

Ethernet controller. The data is then sent to the 4B5B encoder for formatting. The encoded data is then sent to the

scrambler. The scrambled and encoded data is then sent to the TP transmitter. The TP transmitter converts the

encoded and scrambled data into MLT-3 ternary format, preshapes the output, and drives the twisted-pair cable.

On the receive side for 100 Mbits/s TX operation, the twisted-pair receiver receives incoming encoded and scram-

bled MLT-3 data from the twisted pair cable, removes any high-frequency noise, equalizes the input signal to com-

pensate for the effects of the cable, qualifies the data with a squelch algorithm, and converts the data from MLT-3

coded twisted-pair levels to internal digital levels. The output of the twisted-pair receiver then goes to a clock and

data recovery block which recovers a clock from the incoming data, uses the clock to latch in valid data into the

device, and converts the data back to NRZ format. The NRZ data is then unscrambled and decoded by the 4B5B

decoder and descrambler, respectively, and outputted to an external Ethernet controller by the controller interface.

10 Mbits/s operation is similar to 100 Mbits/s TX operation except (1) there is no scrambler/descrambler, (2) the

encoder/decoder is Manchester instead of 4B5B, (3) the data rate is 10 Mbits/s instead of 100 Mbits/s, and (4) the

twisted-pair symbol data is two-level Manchester instead of ternary MLT-3.

The management interface (hereafter referred to as the MI serial port) is a two-pin bidirectional link through which

configuration inputs can be set and status outputs can be read. Each block plus the operating modes is described

in more detail in the following sections. Since the

ET901

can operate as either a 100Base-TX or a 10Base-T

device, each of the following sections describes the performance of the respective section in both 100 Mbits/s and

10 Mbits/s modes.

Status Information

ET901

status information is available on the LED output pins. Transmit activity, receive activity, link status, link

polarity and collision activity information is output to the four LED output pins, selectable via LEDSEL in Rx16

(Rx10h) bit[6:5] as follows.

Table 1. LED Output Pin List (Alphabetical Order)

LEDSEL

LED0

Link/Act

Power/TxAct

Speed 100

Power/TxAct

LED1

Speed

Link/RxAct

Speed 10

Link/RxAct

LED2

Duplex

Speed

Act

Speed

LED3

Collision

Duplex

Collision

Agere Systems - Proprietary

L-ET901-L-DB相似产品对比

	L-ET901-L-DB	L-ET901-L-DT
描述	Ethernet Transceiver, PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48	Ethernet Transceiver, PQFP48, 7 X 7 MM, LEAD FREE, LQFP-48
包装说明	LFQFP,	LFQFP,
Reach Compliance Code	compliant	compliant
JESD-30 代码	S-PQFP-G48	S-PQFP-G48
JESD-609代码	e6	e6
长度	7 mm	7 mm
功能数量	1	1
端子数量	48	48
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260	260
认证状态	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm
标称供电电压	3.3 V	3.3 V
表面贴装	YES	YES
电信集成电路类型	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
温度等级	COMMERCIAL	COMMERCIAL
端子面层	TIN BISMUTH	TIN BISMUTH
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
处于峰值回流温度下的最长时间	40	40
宽度	7 mm	7 mm
Base Number Matches	1	1

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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