IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING BUFFER/LINE DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT INVERTING
BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH16540:
– High Output Drivers: ±24mA
– Suitable for heavy loads
–
–
–
IDT74ALVCH16540
DESCRIPTION:
This 16-bit inverting buffer/line driver is built using advanced dual
metal CMOS technology. The ALVCH16540 offers bus/backplane
interface capability with improved packing density and a flow-through
organization for simplifying board layout. It is designed specifically to
improve the performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and transmitters. The
three-state controls operate this device in a quad-nibble, dual-byte, or
single 16-bit word mode. The 3-state outputs are controlled by the output
enable (OE) pins. A high on OE causes the outputs to force a high
impedance off-state. All inputs are designed with hysteresis for improved
noise margin.
The ALVCH16540 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCH16540 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
A
0
47
2
1
Y
0
2
A
0
36
13
2
Y
0
1
A
1
46
3
1
Y
1
2
A
1
35
14
2
Y
1
1
A
2
44
5
1
Y
2
2
A
2
33
16
2
Y
2
1
A
3
43
6
1
Y
3
2
A
3
32
17
2
Y
3
1
A
4
41
8
1
Y
4
2
A
4
30
19
2
Y
4
1
A
5
40
9
1
Y
5
2
A
5
29
20
2
Y
5
1
A
6
38
11
1
Y
6
2
A
6
27
22
2
Y
6
1
A
7
37
12
1
Y
7
2
A
7
26
23
2
Y
7
1
1
OE
1
48
2
OE
1
24
1
OE
2
2
OE
2
25
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4545/-
IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING BUFFER/LINE DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
1
OE
1
1
Y
0
1
Y
1
1
2
3
4
5
6
7
8
9
10
11
SO48-1
12 SO48-2
SO48-3
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
OE
2
1
A
0
1
A
1
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
Y
2
1
Y
3
GND
1
A
2
1
A
3
V
CC
1
Y
4
1
Y
5
V
CC
1
A
4
1
A
5
GND
1
Y
6
1
Y
7
2
Y
0
2
Y
1
GND
1
A
6
1
A
7
2
A
0
2
A
1
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
GND
2
Y
2
2
Y
3
GND
2
A
2
2
A
3
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
V
CC
2
Y
4
2
Y
5
V
CC
2
A
4
2
A
5
GND
2
Y
6
2
Y
7
2
OE
1
GND
2
A
6
2
A
7
2
OE
2
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
SSOP/TSSOP/TVSOP
TOP VIEW
xOE
1
L
L
X
H
Inputs
xOE
2
L
L
H
X
(1)
xAx
L
H
X
X
Output
xYx
H
L
Z
Z
PIN DESCRIPTION
Pin Names
xOEx
xAx
xYx
Description
3–State Output Enable Inputs (Active LOW)
Data Inputs
3-State Outputs
(1)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
2
IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING BUFFER/LINE DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING BUFFER/LINE DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
V
CC
= 3.3V ± 0.3V
Typical
Unit
pF
pF
—
—
—
—
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK
(o)
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
xOEx to xYx
Output Disable Time
xOEx to xYx
Output Skew
(2)
Min.
(1)
V
CC
= 2.5V ± 0.2V
Max.
Min.
V
CC
= 2.7V
V
CC
= 3.3V ± 0.3V
Min.
1
1
1
Max.
3
3.8
4.1
500
Unit
ns
—
—
—
—
—
—
—
—
—
—
—
—
Max.
3.6
4.7
4.5
ns
ns
ps
—
—
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16540
3.3V CMOS 16-BIT INVERTING BUFFER/LINE DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PHAS E
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORM ALLY
CLOSE D
LOW
t
PZH
OUTPUT
SW ITCH
NORM ALLY
OPEN
HIGH
V
LOAD /2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD /2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OU T
R
T
500
Ω
C
L
ALV C Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
NEW16link
t
R EM
GND
Open
t
S U
t
H
OUTPUT SKEW -
INPUT
TSK
(x)
t
PH L1
V
IH
V
T
0V
V
OH
t
PLH1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
P HL1
ALV C Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
