written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16
. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
Functional Description
The CY7C1021 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
V
SS
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
64K x 16
RAM Array
512 X 2048
I/O
1
– I/O
8
I/O
9
– I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
5
A
6
A
7
OE
BHE
BLE
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
NC
A
8
A
9
A
10
A
11
NC
1021-2
ROW DECODER
Selection Guide
7C1021-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain preliminary information.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
7C1021-12
12
220
5
0.5
7C1021-15
15
220
5
0.5
7C1021-20
20
220
5
0.5
10
Commercial
Commercial
L
220
5
0.5
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 20, 2000
CY7C1021
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
......................................–0.5V to V
CC
+0.5V
DC Input Voltage
[1]
...................................–0.5V to V
CC
+0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
Test Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage V
CC
= Min.,
I
OH
= –4.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
L
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
−0.5
−1
−1
7C1021-10
Min.
2.4
0.4
6.0
0.8
+1
+1
−300
220
2.2
–0.5
–1
–1
Max.
7C1021-12
Min.
2.4
0.4
6.0
0.8
+1
+1
–300
220
2.2
–0.3
–1
–5
Max.
7C1021-15
Min.
2.4
0.4
6.0
0.8
+1
+5
–300
220
2.2
–0.3
–1
–5
Max.
7C1021-20
Min.
2.4
0.4
6.0
0.8
+1
+5
–300
200
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
40
40
40
40
mA
I
SB2
5
0.5
5
0.5
5
0.5
5
0.5
mA
mA
Shaded areas contain preliminary information.
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the case temperature.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C1021
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
R2
255Ω
R 481
Ω
R 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
167
30 pF
R2
255Ω
GND
< 3 ns
3.0V
90%
10%
90%
10%
< 3 ns
ALL INPUT PULSES
(b)
1021-3
1.73V
1021-4
Switching Characteristics
[5]
Over the Operating Range
7C1021-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
[6, 7]
7C1021-12
Min.
12
Max.
7C1021-15
Min.
15
Max.
7C1021-20
Min.
20
Max.
Unit
ns
20
3
20
9
0
9
3
9
0
20
9
0
9
20
12
12
0
0
12
10
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
12
ns
ns
Description
Min.
10
Max.
10
3
10
5
0
5
3
5
0
10
5
0
5
10
8
7
0
0
7
5
0
3
5
7
8
12
9
8
0
0
8
6
0
3
0
0
3
0
3
12
3
12
6
0
6
3
6
0
12
6
0
6
15
10
10
0
0
10
8
0
3
6
9
15
15
7
7
7
15
7
7
OE HIGH to High Z
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
WRITE CYCLE
[8]
7
Shaded areas contain preliminary information.
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
CY7C1021
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1021-5
Read Cycle No. 2 (OE Controlled)
ADDRESS
[10, 11]
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
1021-6
t
HZOE
HIGH
IMPEDANCE
DATA OUT
IICC
CC
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
4
CY7C1021
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
BW
BHE, BLE
t
SD
DATA I/O
t
HD
t
HA
1021-7
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
PWE
WE
t
SCE
CE
t
SD
DATA I/O
t
HD
t
HA
1021-8
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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