CY28325-3
FTG for VIA™ Pentium 4™ Chipsets
Features
•
Spread Spectrum Frequency Timing Generator for VIA
PT/M 266-800 Pentium 4 Chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Selectable hardware or software-programmed clock
frequency when Watchdog Timer time-out
• Capable to generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus Byte Read/Write and Block Read/Write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable-drive strength support
• Programmable-output skew support
• Three copies AGP Clocks
• Power management control inputs
• Available in 48-pin SSOP
CPU
x3
AGP
x3
PCI
x9
REF
x1
APIC
x2
48M
x1
24_48M
x1
Block Diagram
X1
X2
Pin Configuration
VDD_REF
REF
[1]
XTAL
OSC
PLL 1
SSOP-48
*FS4/REF
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS3/48MHz
*FS2/24_48MHz
GND_48MHz
*FS0/PCI_F
*FS1/PCI1
*MULT_SEL1/PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*PD#
AGP0
VDD_AGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_APIC
GND_APIC
APIC0
APIC1
GND_CPU
VDD_CPU_CS(2.5V)
CPUT_CS_F
CPUC_CS_F
CPUT_0
CPUC_0
VDD_CPU(3.3V)
IREF
GND_CPU
CPUT_1
CPUC_1
VTT_PWRGD#
CPU_STOP#*
PCI_STOP#*
RST#
SDATA
SCLK
AGP2
AGP1
GND_AGP
PLL Ref Freq
Divider
Network
Stop
Clock
Control
VDD_CPU_CS (2.5V)
CPUT_CS, CPUC_CS
VDD_CPU (3.3V)
CPUT_0,1, CPUC_0,1
*(FS0:4)
VTT_PWRGD#
*CPU_STOP#
*MULTSEL1
~
VDD_APIC
APIC0:1
VDD_AGP
AGP0:2
CY28325-3
VDD_PCI
PCI_F
PD#
Stop
Clock
Control
PCI1:8
*PCI_STOP#
PLL2
VDD_48MHz
48MHz
24_48MHz
2
SDATA
SCLK
SMBus
Logic
RST#
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
CY28325-3
Pin Definitions
Pin Name
X1
No.
4
Type
I
Description
Crystal Connection or External Reference Frequency Input:
This pin
has dual functions. It can be used as an external 14.318-MHz crystal con-
nection or as an external reference frequency input.
Crystal Connection:
Connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Reference Clock Output/Frequency Select 4:
3.3V 14.318-MHz output.
This pin also serves as a power-on strap option to determine device oper-
ating frequency as described in the Frequency Selection Table.
CPU Clock Outputs:
Frequency is set by the FS0:4 inputs or through
serial input interface.
CPU Clock Outputs for Chipset:
Frequency is set by the FS0:4 inputs or
through serial input interface.
APIC Clock Output:
APIC clock outputs running at half of PCI output
frequency.
AGP Clock Output:
3.3V AGP clock.
Free-running PCI Output 1/Frequency Select 1:
3.3V free-running PCI
output. This pin also serves as a power-on strap option to determine
device operating frequency as described in the Frequency Selection Table.
PCI Output 1 /Frequency Select 1:
3.3V PCI output. This pin also serves
as a power-on strap option to determine device operating frequency as
described in the Frequency Selection Table.
PCI Output 2/Current Multiplier Selection 1:
3.3V PCI output. This pin
also serves as a power-on strap option to determine the current multiplier
for the CPU clock outputs. The MULTSEL definitions are as follows:
MULTISEL
0 = Ioh is 4 × IREF
1 = Ioh is 6 × IREF
PCI Clock Output 3 to 8:
3.3V PCI clock outputs.
48-MHz Output/Frequency Select 3:
3.3V fixed 48-MHz, non-spread
spectrum output. This pin also serves as a power-on strap option to deter-
mine device operating frequency as described in the Frequency Selection
Table.
24- or 48-MHz Output/Frequency Select 2:
3.3V fixed 24- or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap
option to determine device operating frequency as described in the Fre-
quency Selection Table.
CPU Output Control:
3.3V LVTTL-compatible input that disables
CPUT_CS, CPUC_CS, CPUT_0:1 and CPUC_0:1.
PCI Output Control:
3.3V LVTTL-compatible input that disables PCI1:8.
Power-down Control:
3.3V LVTTL-compatible input that places the
device in power down mode when held LOW.
SMBus Clock Input:
Clock pin for serial interface.
SMBus Data Input:
Data pin for serial interface.
X2
REF/FS4
5
1
O
I/O
CPUT_0:1
CPUC_0:1
CPUT_CS_F
CPUC_CS_F
APIC0:1
AGP 0:2
PCI_F/FS0
40, 39, 35, 34
42, 41
46, 45
23, 26, 27
10
O
O
O
O
I/O
PCI1/FS1
11
I/O
PCI2/MULTSEL1
12
I/O
PCI3:8
48MHz/FS3
14, 15, 17, 18,
19, 21
7
O
I/O
24_48MHz/FS2
8
I/O
CPU_STOP#
PCI_ST0P#
PD#
SCLK
SDATA
RST#
IREF
32
31
22
28
29
30
37
I
I
I
I
I/O
O
System Reset Output:
Open-drain system reset output.
(open-drain)
I
Current Reference for CPU output:
A precision resistor is attached to
this pin, which is connected to the internal current reference.
Rev 1.0, November 21, 2006
Page 2 of 18
CY28325-3
Pin Definitions
(continued)
Pin Name
VTT_PWRGD#
No.
33
Type
I
Description
Power-good from Voltage Regulator Module (VRM):
3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4
and MULTSEL inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
2.5V Power Connection:
Power supply for CPU_CS outputs buffers and
APIC output buffers. Connect to 2.5V.
3.3V Power Connection:
Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and 48-MHz
output buffers. Connect to 3.3V.
VDD_CPU_CS,
VDD_APIC
VDD_REF,
VDD_48MHz,
VDD _PCI,
VDD_AGP,
VDD_CPU
GND_REF
GND_48MHz,
GND_PCI,
GND_AGP,
GND_CPU,
GND_APIC
43, 48
2, 6, 16, 24, 38
P
P
3, 9, 13, 20, 25,
36, 44, 47
G
Ground Connection:
Connect all ground pins to the common system
ground plane.
Table 1. Frequency Selection Table
Input Conditions
FS4
SEL4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
FS3
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
FS2
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
FS1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
102.0
105.0
108.0
111.0
114.0
117.0
120.0
123.0
126.0
130.0
136.0
140.0
144.0
148.0
152.0
156.0
160.0
164.0
166.6
170.0
175.0
180.0
AGP
68.0
70.0
72.0
74.0
76.0
78.0
80.0
82.0
63.0
65.0
68.0
70.0
72.0
74.0
76.0
78.0
80.0
82.0
66.6
68.0
70.0
72.0
PCI
34.0
35.0
36.0
37.0
38.0
39.0
40.0
41.0
31.5
32.5
34.0
35.0
36.0
37.0
38.0
39.0
40.0
41.0
33.3
34.0
35.0
36.0
APIC
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
18.0
18.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
20.5
16.7
17.0
17.5
18.0
Output Frequency
PLL Gear
Constants
(G)
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Rev 1.0, November 21, 2006
Page 3 of 18
CY28325-3
Table 1. Frequency Selection Table
(continued)
Input Conditions
FS4
SEL4
1
1
1
1
1
1
1
1
1
1
FS3
SEL3
0
0
1
1
1
1
1
1
1
1
FS2
SEL2
1
1
0
0
0
0
1
1
1
1
FS1
SEL1
1
1
0
0
1
1
0
0
1
1
FS0
SEL0
0
1
0
1
0
1
0
1
0
1
CPU
185.0
190.0
100.9
133.9
200.5
166.8
100.0
133.3
200.0
166.7
AGP
74.0
76.0
67.3
67.0
66.8
66.7
66.6
66.6
66.6
66.7
PCI
37.0
38.0
33.6
33.5
33.4
33.3
33.3
33.3
33.3
33.3
APIC
18.5
19.0
16.8
16.7
16.7
16.7
16.7
16.7
16.7
16.7
Output Frequency
PLL Gear
Constants
(G)
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Swing Select Functions
MultSEL1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MultSEL0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
50
60
50
60
50
60
50
60
50
60
50
60
50
60
50 Ohm
60 Ohm
Reference R, IREF =
VDD/(3*Rr)
Output
Current
I
OH
= 4*Iref
I
OH
= 4*Iref
I
OH
= 5*Iref
I
OH
= 5*Iref
I
OH
= 6*Iref
I
OH
= 6*Iref
I
OH
= 7*Iref
I
OH
= 7*Iref
I
OH
= 4*Iref
I
OH
= 4*Iref
I
OH
= 5*Iref
I
OH
= 5*Iref
I
OH
= 6*Iref
I
OH
= 6*Iref
I
OH
= 7*Iref
I
OH
= 7*Iref
V
OH
@ Z
1.0V @ 50
1.2V @ 60
1.25V @ 50
1.5V @ 60
1.5V @ 50
1.8V @ 60
1.75V @ 50
2.1V @ 60
0.47V @ 50
0.56V @ 60
0.58V @ 50
0.7V @ 60
0.7V @ 50
0.84V @ 60
0.81V @ 50
0.97V @ 60
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32 mA
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Rev 1.0, November 21, 2006
Page 4 of 18
CY28325-3
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
T
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
Block Read Protocol
Description
Rev 1.0, November 21, 2006
Page 5 of 18
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
