PRELIMINARY DATASHEET
LOW EMI CLOCK GENERATOR
Description
The IDT5P50003 generates a low EMI output clock from a
clock input. The part is designed to dither the LCD interface
clock for flat panel graphics controllers. The device uses
IDT’s proprietary mix of analog and digital Phase Locked
Loop (PLL) technology to spread the frequency spectrum of
the output, thereby reducing the frequency amplitude peaks
by several dB.
IDT offers many other clocks for computers and computer
peripherals. Consult us when you need to remove crystals
and oscillators from your board.
IDT5P50003
Features
•
•
•
•
•
•
•
Packaged in 8-pin MSOP
Available in Pb-free, RoHS 6 compliant package
Industrial temperature range available
Provides a spread spectrum output clock
Supports flat panel controllers
Guaranteed to +85° C operation
Accepts a clock input, provides same frequency dithered
output
•
Good for all VGA modes from 10 to 65 MHz
•
Peak reduction by 7dB - 14dB typical on 3rd - 19th odd
harmonics
•
•
•
•
Low EMI feature can be disabled
Includes Power-down
Operating voltage of 1.5 - 2.5 V
Advanced, low-power CMOS process
Block Diagram
VDD
S2:0
3
Crystal or
Clock input
X1/ICLK
X2
Capacitors required
with crystal input
Crystal
Oscillator/
Buffer
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
CLK
GND
IDT™
LOW EMI CLOCK GENERATOR
1
IDT5P50003
REV A 101206
IDT5P50003
LOW EMI CLOCK GENERATOR
SSCG
Pin Assignment
X1/ICLK
VDD
GND
CLK
1
2
3
4
8-pin MSOP
8
7
6
5
X2
S1
S0
S2
Spread Direction and Percentage
Select Table
S2
Pin 5
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
S1
Pin 7
0
0
0
M
M
M
1
1
1
0
0
0
M
M
M
1
1
1
S0
Pin 6
0
M
1
0
M
1
0
M
1
0
M
1
0
M
1
0
M
1
Spread
Direction
Down
Down
Down
Down
Down
Down
Down
Down
Power Down
Center
Center
Center
Center
Center
Center
Center
Center
No spread
Spread
Percentage (%)
-0.25
-0.50
-0.60
-0.80
-1.0
-1.50
-2
-3
—
±0.25
±0.35
±0.50
±0.70
±0.80
±1.0
±1.5
±2.0
0
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Pin Descriptions
Pin
Number
Pin Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/ICLK
VDD
GND
CLK
S2
S0
S1
X2
Input
Power
Power
Output
Input
Input
Input
Output
Connect to crystal or clock input.
Connect to +3.3 V.
Connect to ground.
Spread spectrum clock output per table above.
Function select 2 input. Selects spread amount and direction per table above.
Internal pull-up resistor.
Function select 0 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 1 input. Selects spread amount and direction per table above.
Internal mid-level.
Crystal connection. Float for clock input.
IDT™
LOW EMI CLOCK GENERATOR
2
IDT5P50003
REV A 101206
IDT5P50003
LOW EMI CLOCK GENERATOR
SSCG
External Components
The IDT5P50003 requires a minimum number of external
components for proper operation.
Powerup Considerations
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken while
utilizing the IDT5P50003.
1. An input signal should not be applied to ICLK until VDD is
stable (within 10% of its final value). This requirement can
easily be met by operating the IDT5P50003 and then ICLK
source from the same power supply.
2. If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes at
the new frequency.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3, as close to these
pins as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50Ω trace (a commonly used trace impedance),
place a 33Ω resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω
.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have three
separate states to make the selections shown in the table on
page 2. To select the M (mid) level, the connection to these
pins must be eliminated by either floating them originally, or
tri-stating the GPIO pins which drive the select pins.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5P50003. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
IDT™
LOW EMI CLOCK GENERATOR
3
IDT5P50003
REV A 101206
IDT5P50003
LOW EMI CLOCK GENERATOR
SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P50003. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +85° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+1.4
Typ.
Max.
+85
+2.7
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 1.8 V,
Ambient Temperature 0 to +85° C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Symbol
VDD
IDD
IDDPD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
C
IN
Conditions
No load, at 1.8 V
S0=S1=SD=1
ICLK
ICLK
S2, S1, S0
S2, S0, S1
I
OH
= -12 mA
I
OL
= -12 mA
S2, S0, S1
Min.
1.65
Typ.
10
60
Max.
1.95
Units
V
mA
µA
V
(VDD/2)+1
0.65VDD
VDD/2
VDD/2
(VDD/2)-1
0.35VDD
V
V
V
V
V
pF
VDD-0.45
0.45
5
IDT™
LOW EMI CLOCK GENERATOR
4
IDT5P50003
REV A 101206
IDT5P50003
LOW EMI CLOCK GENERATOR
SSCG
AC Electrical Characteristics
Unless stated otherwise,
VDD = 1.8 V,
Ambient Temperature 0 to +85° C
Parameter
Input/Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Modualtion Frequency
EMI Peak Frequency Reduction
Symbol
Conditions
Time above VDD/2
Min.
10
20
40
Typ.
Max. Units
65
80
MHz
%
%
ns
ns
41
kHz
dB
50
1.0
1.0
60
t
OR
t
OF
20% to 80%
80% to 20%
19
3rd - 19th odd
harmonics
7 to 14
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
Marking Diagram
TBD
Notes:
1. “Z” is the device step (1 to 2 characters).
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “G” after the two-letter package code designates RoHS compliant package.
5. “I” at the end of part number indicates industrial temperature range.
6. Bottom marking: country of origin if not USA.
IDT™
LOW EMI CLOCK GENERATOR
5
IDT5P50003
REV A 101206
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
