74VHC4046 CMOS Phase Lock Loop
April 1994
Revised October 2003
74VHC4046
CMOS Phase Lock Loop
General Description
The VHC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high fre-
quency operation both in the phase comparator and VCO
sections. This device contains a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The three phase comparators have a
common signal input and a common comparator input. The
signal input has a self biasing amplifier allowing signals to
be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard input
logic levels. This device is similar to the CD4046 except
that the Zener diode of the metal gate CMOS device has
been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It pro-
vides a digital error signal that maintains a 90 phase shift
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input fre-
quency than phase comparator I, but provides better noise
rejection.
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STATE output that provides a signal that locks the VCO
output signal to the input signal with 0 phase shift between
them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto har-
monics than the other two comparators.
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components connected
to the C1
A
, C1
B
, R
1
and R
2
pins. An inhibit pin is provided
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is con-
nected to the VCO input and whose drain connects the
Demodulator output. This output normally is used by tying
a resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Features
s
Low dynamic power consumption:
s
Maximum VCO operating frequency:
(V
CC
=
4.5V)
s
Fast comparator response time (V
CC
=
4.5V)
Comparator I:
Comparator II:
Comparator III:
25 ns
30 ns
25 ns
(V
CC
=
4.5V)
12 MHz
s
VCO has high linearity and high temperature stability
s
Pin and function compatible with the 74HC4046
Ordering Code:
Order Number
74VHC4046M
74VHC4046MTC
74VHC4046N
Package Number
M16A
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS011675
www.fairchildsemi.com
74VHC4046
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current per pin (I
OUT
)
DC V
CC
or GND Current,
per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
(Note 4)
Conditions
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
2
0
Max
6
V
CC
Units
V
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V
−
0.5 to V
CC
+
0.5V
±
20 mA
±
25 mA
±
50 mA
−
65
°
C
+
150
°
C
600 mW
500 mW
−
40
+
85
1000
500
400
°
C
ns
ns
ns
Note 1:
Maximum Ratings are those values beyond which damage to the
device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
=25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
20
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
50
±0.25
30
600
40
750
T
A
=−40
to 85°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
±2.5
65
1200
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
2.0V
4.5V
6.0V
4.5V
6.0V
2.0V
4.5V
6.0V
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
4.5V
6.0V
6.0V
6.0V
6.0V
6.0V
6.0V
I
IN
I
IN
I
OZ
I
CC
Maximum Input Current (Pins 3,5,9) V
IN
=
V
CC
or GND
Maximum Input Current (Pin 14)
Maximum 3-STATE Output
Leakage Current (Pin 13)
Maximum Quiescent Supply
Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
V
IN
=
V
CC
or GND
Pin 14 Open
V
IN
=
V
CC
or GND
V
OUT
=
V
CC
or GND
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for VHC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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