White Electronic Designs
WV3HG264M72EEU-D4
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
FEATURES
200-pin SO-DIMM, dual in-line memory module
Fast data transfer rates: PC2-4200 and PC2-3200
V
CC
= V
CCQ
= 1.8V ±0.1V
1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 200 Pin SO-DIMM
• PCB – 31.75mm (1.25") Max
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3HG264M72EEU is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
August 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
V
REF
V
SS
DQ0
DQ4
DQ1
DQ5
V
SS
V
SS
DQS0#
DM0
DQS0
V
SS
V
SS
DQ6
DQ2
DQ7
DQ3
V
SS
V
SS
DQ12
DQ8
DQ13
DQ9
V
SS
V
SS
DM1
DQS1#
V
SS
DQS1
DQ14
V
SS
DQ15
DQ10
V
SS
DQ11
NC
V
SS
DQ20
DQ16
DQ21
DQ17
V
SS
V
SS
DM2
DQS2#
V
SS
DQS2
DQ22
V
SS
DQ23
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
DQ18
V
SS
DQ19
DQ28
V
SS
DQ29
DQ24
V
SS
DQ25
DM3
V
SS
V
SS
DQS3#
DQ30
DQS3
DQ31
V
SS
V
SS
DQ26
CB4
DQ27
CB5
V
SS
V
SS
CB0
DM8
CB1
V
SS
V
SS
CB6
DQS8#
CB7
DQS8
V
CC
V
SS
CKE1
CB2
CKE0
CB3
V
CC
V
CC
A12
NC
A9
A11
V
CC
A7
A8
V
CC
A6
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A5
V
CC
A4
A3
A2
A1
V
CC
V
CC
V
SS
CK0
V
SS
CK0#
A10/AP
V
CC
BA0
A0
WE#
BA1
V
CC
RAS#
CAS#
V
CC
S1#
S0#
ODT1
ODT0
V
SS
A13
(3)
DQ32
V
CC
DQ33
DQ36
V
SS
DQ37
DQS4#
V
SS
DQS4
DM4
V
SS
V
SS
DQ34
DQ38
DQ35
DQ39
V
SS
V
SS
DQ40
DQ44
DQ41
DQ45
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
V
SS
V
SS
DQS5#
DM5
DQS5
V
SS
V
SS
DQ46
DQ42
DQ47
DQ43
V
SS
V
SS
DQ52
DQ48
DQ53
DQ49
V
SS
V
SS
DM6
DQS6#
V
SS
DQS6
DQ54
V
SS
DQ55
DQ50
V
SS
DQ51
DQ60
V
SS
DQ61
DQ56
V
SS
DQ57
DM7
V
SS
V
SS
DQS7#
DQ62
DQS7
DQ63
V
SS
V
CC
SPD
DQ58
SA0
DQ59
SA1
SDA
SCL
WV3HG264M72EEU-D4
ADVANCED
PIN NAMES
Pin Name
A0-A9, A11-A13
A10/AP
BA0, BA2
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
S0#, S1#
RAS#
CAS#
WE#
V
CC
V
CCQ
V
SS
SA0-SA2
SDA
V
REF
DM0-DM8
V
CCSPD
SCL
Function
Address Inputs
Address Input/Auto Precharge
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes negative
On-die termination control
Clock inputs, positive/negative
Clock enable input
Chip select input
Row Address Strobe
Column Address Strobe
Write Enable
Core Power (1.8V)
I/O Power (1.8V)
Ground
SPD address
Serial Data Input/Output
Input/Output Reference
Data-in mask
Serial EEPROM power supply
Serial Presence Detect(SPD) Clock Input
NOTES:
SA2 does NOT connect to memory connector and is shown ONLY on Block Diagram
SA2 is tied LOW on memory module for all memory configurations
August 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG264M72EEU-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
S1#
S0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS8#
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
Serial PD
SCL
WP A0
A1
A2
SDA
SA0 SA1 SA2
V
CCSPD
V
CC
/V
CCQ
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
S0#
S1#
BA0 - BA1
A0 - A12
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
S0# : DDR2 SDRAMs
S1# : DDR2 SDRAMs
BA0 - RBA1 : DDR2 SDRAMs
A0 - A12 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
V
REF
V
SS
120Ω
CK0
CK0#
RESET#
PLL
CK
CK#
NOTE: All resistor values are 22 ohms unless otherwise specified.
August 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Rating
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
Symbol
V
CC
V
CCL
V
CCQ
V
REF
V
TT
Min.
1.7
1.7
1.7
0.49*V
CCQ
V
REF
-0.04
Type
1.8
1.8
1.8
0.50*V
CCQ
V
REF
WV3HG264M72EEU-D4
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS (SSTL_1.8V)
Max.
1.9
1.9
1.9
0.51*V
CCQ
V
REF
+0.04
Units
V
V
V
V
V
Notes
4
4
1, 2
3
There is no specific device V
CC
supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
CCQ
must be less than or equal to V
CC
.
1. The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
REF
isexpected to be about 0.5 x V
CCQ
of the transmitting
device and V
REF
is expected to track variations in V
CCQ
.
2. Peak to peak AC noise on V
REF
may not exceed ±2% V
REF
(DC).
3. V
TT
of transmitting device must track V
REF
of receiving device.
4. AC parameters are measured with V
CC
, V
CCQ
and V
CCDL
tied together.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Supply Voltage relative to V
SS
Short Circuit Output Current
Power Dissipation
Symbol
V
T
V
CC
I
OS
P
D
Rating
-0.5 to +2.3
-0.5 to +2.3
50
18 (Max)
Units
V
V
mA
W
ENVIRONMENTAL
Parameter
Operating Case Temperature
(1)
Operating Humidity (relative)
Storage Temperature
Storage Humidity (without condensation)
Symbol
T
OPR
H
OPR
T
STG
T
STG
Rating
0 to +85
10 to 90
-55 to +100
5 to 95
Units
°C
%
°C
%
NOTE:
1. Case Temperature is the case surface temperature on the center/top side of SDRAMs. For the measurement condition, please refer to JESD51-2 standard
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= V
CCQ
= 1.8V
Parameter
Control Signal Input Capacitance
Control Signal Input Capacitance
Clock Input Capacitance
Data & DQSI/O Capacitance
NOTE:
1. PLL component specificatiion
Symbol
C
I1
C
I2
C
I3
C
O
Pins
Address, RAS#, CAS#, WE#
CS#, CKE, ODT
CK, CK#
DQ, DQS, DQS#, DM, CB
Min
20.5
11.5
2
7.5
Max
38.5
20.5
3
10.5
Unit
pF
pF
pF
pF
Note
(1)
August 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG264M72EEU-D4
ADVANCED
DDR2 I
DD
SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
0°C ≤ T
CASE
< +70°C; V
CCQ
= + 1.8V ± 0.1V, V
CC
= +1.8V ± 0.1V
Symbol
I
DD0
Proposed Conditions
Operating one bank active-precharge current;
t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RAS
= t
RAS
min(I
DD
); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RAS
= t
RAS
min(I
DD
), t
RCD
= t
RCD
(I
DD
);
CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as I
DD
4W
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
DD
); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE;
Data bus inputs are FLOATING
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
DD
); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
534
1,530
403
1,440
Units
mA
I
DD1
1,620
1,485
mA
I
DD2P
144
144
mA
I
DD2Q
450
450
mA
I
DD2N
540
540
270
1,260
540
540
270
1,170
mA
mA
mA
mA
I
DD3P
I
DD3N
Active standby current;
All banks open; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RAS
=
t
RAS
max(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as I
DD
4W
Burst auto refresh current;
t
CK
= t
CK
(I
DD
); Refresh command at every t
RFC
(I
DD
) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL(I
DD
), AL = t
RC
D(I
DD
)-1*t
CK
(I
DD
); t
CK
= t
CK
(I
DD
), t
RC
=
t
RC
(I
DD
), t
RRD
= t
RRD
(I
DD
), t
RCD
= 1*t
CK
(I
DD
); CKE is HIGH, CS\ is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as I
DD4R
; Refer to the following page for
detailed timing conditions
I
DD4W
2,430
1,890
mA
I
DD4R
2,250
1,890
mA
I
DD5B
2,385
2,250
mA
I
DD6
99
99
mA
I
DD7
3,105
3,015
mA
Note: I
DD
specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
August 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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