Hitachi SuperH™ RISC engine
SH7014, SH7016,
SH7017F-ZTAT™
Hardware Manual
ADE-602-128C
Rev. 4.0
3/18/00
Hitachi, Ltd.
Cautions
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contained in this document.
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have received the latest product standards or specifications before final design, purchase or
use.
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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semiconductor products.
Preface
The SH7014/16/17 CMOS single-chip microprocessors integrate a Hitachi-original architecture,
high-speed CPU with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle,
which greatly improves instruction execution speed. In addition, the 32-bit internal-bus
architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds. In
particular, this LSI has a 1-kbyte on-chip cache, which allows an improvement in CPU
performance during external memory access.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial
communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory
or peripheral LSIs can be connected efficiently with an external memory access support function.
This greatly reduces system cost.
This LSI has an F-ZTAT
TM
version with on-chip flash memory and a mask ROM version. These
versions enable users to respond quickly and flexibly to changing application specifications,
growing production volumes, and other conditions.
This hardware manual covers the SH7014/16/17/. For a detailed description of instructions, refer
to the programming manual.
Related Manuals
SH7014/16/17 instruction execution:
SH-1/SH-2/SH-DSP Programming Manual
For information on development systems, please contact a Hitachi sales representative.
Contents
Section 1
1.1
1.2
1.3
1
SH7014/16/17 Overview ...................................................................................................
1
1.1.1 SH7014/16/17 Series Features .............................................................................
1
Block Diagram...................................................................................................................
6
Pin Arrangement and Pin Functions .................................................................................. 8
1.3.1 Pin Arrangment.....................................................................................................
8
1.3.2 Pin Arrangement by Mode ................................................................................... 10
1.3.3 Pin Functions ........................................................................................................ 14
SH7014/16/17 Overview
..............................................................................
Section 2
2.1
CPU
..................................................................................................................... 19
19
19
20
21
21
22
22
22
22
23
23
26
30
33
46
46
48
2.2
2.3
2.4
2.5
Register Configuration.......................................................................................................
2.1.1 General Registers (Rn) .........................................................................................
2.1.2 Control Registers ..................................................................................................
2.1.3 System Registers...................................................................................................
2.1.4 Initial Values of Registers ....................................................................................
Data Formats......................................................................................................................
2.2.1 Data Format in Registers ......................................................................................
2.2.2 Data Format in Memory .......................................................................................
2.2.3 Immediate Data Format ........................................................................................
Instruction Features ...........................................................................................................
2.3.1 RISC-Type Instruction Set ...................................................................................
2.3.2 Addressing Modes ................................................................................................
2.3.3 Instruction Format.....................................................................................................
Instruction Set by Classification ........................................................................................
Processing States ...............................................................................................................
2.5.1 State Transitions ...................................................................................................
2.5.2 Power-Down State ................................................................................................
Section 3
3.1
3.2
3.3
Operating Modes
............................................................................................. 51
Operating Modes, Types, and Selection ............................................................................ 51
Explanation of Operating Modes....................................................................................... 52
Pin Configuration............................................................................................................... 52
Section 4
4.1
4.2
Clock Pulse Generator (CPG)
..................................................................... 53
53
53
53
53
56
i
Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
Oscillator............................................................................................................................
4.2.1 Connecting a Crystal Oscillator............................................................................
4.2.2 External Clock Input Method ...............................................................................
4.2.3
Prescaler ...............................................................................................................
56
Section 5
5.1
Exception Processing
..................................................................................... 57
57
57
58
59
61
61
62
63
63
63
64
64
65
65
66
66
66
66
67
68
68
68
68
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Overview............................................................................................................................
5.1.1 Types of Exception Processing and Priority.........................................................
5.1.2 Exception Processing Operations .........................................................................
5.1.3 Exception Processing Vector Table .....................................................................
Resets.................................................................................................................................
5.2.1 Power-on Reset.....................................................................................................
Address Errors ...................................................................................................................
5.3.1 Address Error Exception Processing ....................................................................
Interrupts ............................................................................................................................
5.4.1 Interrupt Priority Level.........................................................................................
5.4.2 Interrupt Exception Processing.............................................................................
Exceptions Triggered by Instructions ................................................................................
5.5.1 Trap Instructions...................................................................................................
5.5.2 Illegal Slot Instructions.........................................................................................
5.5.3 General Illegal Instructions...................................................................................
When Exception Sources Are Not Accepted.....................................................................
5.6.1 Immediately after a Delayed Branch Instruction..................................................
5.6.2 Immediately after an Interrupt-Disabled Instruction ............................................
Stack Status after Exception Processing Ends...................................................................
Notes on Use ......................................................................................................................
5.8.1 Value of Stack Pointer (SP)..................................................................................
5.8.2 Value of Vector Base Register (VBR) .................................................................
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ......
Section 6
6.1
Interrupt Controller (INTC)
......................................................................... 69
69
69
69
71
71
72
72
72
73
73
76
76
78
79
80
6.2
6.3
6.4
ii
Overview............................................................................................................................
6.1.1 Features.................................................................................................................
6.1.2 Block Diagram......................................................................................................
6.1.3 Pin Configuration .................................................................................................
6.1.4 Register Configuration .........................................................................................
Interrupt Sources................................................................................................................
6.2.1 NMI Interrupts ......................................................................................................
6.2.2 IRQ Interrupts.......................................................................................................
6.2.3 On-Chip Peripheral Module Interrupts.................................................................
6.2.4 Interrupt Exception Vectors and Priority Rankings .............................................
Description of Registers.....................................................................................................
6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)...................................................
6.3.2 Interrupt Control Register (ICR) ..........................................................................
6.3.3 IRQ Status Register (ISR) ....................................................................................
Interrupt Operation.............................................................................................................
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