Features
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Processor Bus Frequency Up to 66 MHz and 83.3 MHz
64-bit Data Bus and 32-bit Address Bus
L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes
Provides Support for Either Asynchronous SRAM, Burst SRAM
or Pipelined Burst SRAM
Compliant with PCI Specification, Revision 2.1
PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible
IEEE 1149.1-compliant, JTAG Boundary-scan Interface
P
D
Max = 1.7 Watts (66 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes Reduce Power Consumption
Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards
Upscreenings Based on Atmel Standards
Full Military Temperature Range (-55°C
≤
T
C
≤
+125°C)
Industrial Temperature Range (-40°C
≤
T
C
≤
+110°C)
V
CC
= 3.3V ± 5%
Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI)
(CI-CGA) Package
PCI Bridge/
Memory
Controller
TSPC106
Description
The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-com-
patible interface between a 60x processor, a secondary (L2) cache or up to a total of
four additional 60x processors, the PCI bus and main memory.
PCI support allows system designers to rapidly design systems using peripherals
already designed for PCI.
The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full
interface compatibility with TTL devices.
The TSPC106 integrates system testability and debugging features via JTAG bound-
ary-scan capability.
Note:
In this document, the term “60x” is used to denote a 32-bit microprocessor from the
PowerPC family that conforms to the bus interface of the PowerPC 601
®
, PowerPC
603
™
or PowerPC 604
™
microprocessors. This does not include the PowerPC 602
™
microprocessor that has a multiplexed address/data bus. 60x processors implement
the PowerPC architecture as it is specified for 32-bit addressing, providing 32-bit effec-
tive (logical) addresses, integer data types of 8, 16 and 32 bits, and floating-point data
types of 32 and 64 bits (single-precision and double-precision).
Rev. 2102A–06/01
1
Figure 1.
TSPC106 Block Diagram
L2 Cache
Interface
Memory
Interface
Power Management
60x Processor
Interface
Error/Interrupt
Control
Target
Master
Configuration
Registers
PCI Interface
Functional Description
The TSPC106 provides a PowerPC microprocessor
CHRP-compliant bridge between the PowerPC micropro-
c es s o r fa m i l y a n d t he P CI b u s . CH RP i s a s e t o f
specifications that defines a unified personal computer
architecture and brings the combined advantages of the
Power Macintosh platform and the standard PC environ-
ment to both system vendors and users. PCI support
allows system designers to rapidly design systems using
peripherals already designed for PCI and other standard
interfaces available in the personal computer hardware
environment. These open specifications make it easier for
system vendors to design computers capable of running
multiple operating systems. The TSPC106 integrates sec-
ondary cache control and a high-performance memory
controller. The TSPC106 uses an advanced 3.3V CMOS
process technology and is fully compatible with TTL
devices.
The TSPC106 supports a programmable interface to a vari-
ety of PowerPC microprocessors operating at select bus
speeds. The 60x address bus is 32 bits wide; the data bus
is 64 bits wide. The 60x processor interface of the
TSPC106 uses a subset of the 60x bus protocol, support-
ing single-beat and burst data transfers. The address and
data buses are decoupled to support pipelined
transactions.
The TSPC106 provides support for the following configura-
tions of 60x processors and L2 cache:
• Up to four 60x processors with no L2 cache
• A single 60x processor plus a direct-mapped, lookaside
L2 cache using the internal L2 cache controller of the
TSPC106
• Up to four 60x processors plus an externally controlled
L2 cache (e.g., the Motorola MPC2604GA integrated L2
lookaside cache)
The memory interface controls processor and PCI interac-
tions to main memory and is capable of supporting a
variety of configurations using DRAM, EDO, or SDRAM
and ROM or Flash ROM.
2
TSPC106
TSPC106
The PCI interface of the TSPC106 complies with the PCI
local bus specification Revision 2.1 and follows the guide-
lines in the PCI System Design Guide Revision 1.0 for host
bridge architecture. The PCI interface connects the proces-
sor and memory buses to the PCI bus to which I/O
components are connected. The PCI bus uses a 32-bit
multiplexed address/data bus plus various control and error
signals.
The PCI interface of the TSPC106 functions as both a mas-
ter and target device. As a master, the 106 supports read
and write operations to the PCI memory space, the PCI I/O
space and the PCI configuration space. The TSPC106 also
supports PCI special-cycle and interrupt-acknowledge
commands. As a target, the TSPC106 supports read and
write operations to system memory.
The TSPC106 provides hardware support for four levels of
power reduction: doze, nap, sleep and suspend. The
design of the TSPC106 is fully static, allowing internal logic
states to be preserved during all power saving modes.
3
Pin Description
Figure 2.
TSPC106 in 303-ball CBGA Package
16
W
DL26
15
DL28
14
DL30
13
DH31
12
DH29
11
DH27
10
DH25
9
DH23
8
DH21
7
DH19
6
DH17
5
DH15
4
DH13
3
DH11
2
DH9
1
DH7
V
DL24
DL27
DL29
DL31
DH30
DH28
DH26
DH24
DH20
DH18
DH16
DH14
DH12
DH10
DH8
DL22
U
MA1/
SDBA0/
AR9
MA2/
SDMA2/
AR10
MA3/
SDMA3/
AR11
MA5/
SDMA5/
AR13
MA6/
SDMA6/
AR14
MA8/
SDMA8/
AR16
DL23
DL25
DL14
PLL2
PLL0
DL12
DL10
DL4
DL2
DL0
DOE/
DBGL2
DBG1
DH6
DL21
DL20
T
WE
DH0
DL15
PLL3
PLL1
DL13
DL11
DL3
DL1
TV/
BR2
BA0/
BR3
HIT
DIRTY_IN/
BR1
ADS/
DALE/
BRL2
DWE0/
DBG2
DL19
DCS/
BG3
R
RCS0
DH2
DH1
DL16
VSS
VDD
DL9
DL5
VSS
VDD
TWE/
BG2
DIRTY_OUT/
BG1
BA1/
BAA
BGL2
A0
TS
P
MA4/
SDMA4/
AR12
MA0/
SDBA1/
SDMA0/
AR0
MA7/
SDMA7/
AR15
MA9/
SDMA9/
AR17
DH4
DH3
VSS
VDD
VSS
DL8
DL6
VDD
VSS
VDD
A1
XATS/
SDMA1
N
DL17
DH5
VDD
VSS
VDD
DL7
DH22
VSS
VDD
VSS
LBCLAIM
CI
A2
TA
M
RAS0/
CS0
DL18
VSS
VDD
VSS
NC
NC
VDD
VSS
VDD
WT
GBL
A3
TT4
L
HRST
QACK
RAS1/
CS1
VDD
CKO/
DWE2
RAS5/
CS5
VSS
VDD
VSS
SYSCLK
DBG0
TBST
BR0
A4
TT3
K
MA11/
MA10/
SDMA11/ SDMA10/
AR19
AR18
MA12/
SDMA12/
AR20
CAS0/
DQM0
RAS3/
CS3
RAS2/
CS2
RAS4/
CS4
RAS7/
CS7
VDD
AVDD
VSS
VDD
A9
A8
A7
BG0
A5
TT2
J
PPEN
RCS1
RAS6/
CS6
MCP
DBGLB/
CKE
VSS
VDD
VSS
A11
A6
A13
A12
A10
TEA
H
QREQ
CAS1/
DQM1
SUS-
PEND
TRST
VSS
DWE1/
DBG3
PIRQ/
SDRAS
NC
NC
VDD
VSS
VDD
A15
A14
A16
TT1
G
CAS2/
DQM2
RTC
CAS4/
DQM4
CAS5/
DQM5
VDD
LSSD_
MODE
VDD
PAR
LOCK
VSS
VDD
VSS
TSIZ1
TSIZ0
A17
TT0
F
BCTL0
BCTL1
CAS6/
DQM6
TCK
VSS
VDD
VSS
PERR
DEV-
SEL
VDD
VSS
VDD
A21
TSIZ2
ARTRY
A18
E
CAS3/
DQM3
NMI
CAS7/
DQM7
MDLE/
SDCAS
TDO
VSS
VDD
SERR
IRDY
VSS
VDD
A31
A29
A22
A20
A19
D
PAR0/
AR1
PAR2/
AR3
PAR1/
AR2
TMS
FOE
AD28
AD24
AD21
AD17
AD14
AD10
C/BE0
AD4
AD0
A30
AACK
A23
C
PAR3/
AR4
PAR5/
AR6
AD30
AD26
AD23
AD19
C/BE2
C/BE1
AD12
AD8
AD6
AD2
A27
A25
A24
B
PAR4/
AR5
PAR7/
AR8
AD1
TDI
AD7
AD11
AD15
TRDY
AD18
AD22
AD25
AD29
REQ
ISA_MASTER/
BERR
A28
A26
A
PAR6/
AR7
GNT
AD3
AD5
AD9
AD13
FRAME
STOP
AD16
AD20
C/BE3
AD27
AD31
FLSHREQ
MEMACK
4
TSPC106
TSPC106
Pinout
Table 1.
TSPC106 Pinout in 303-ball CBGA Package
Signal Name
Pin Number
60x Processor Interface Signals
A[0:31]
AACK
ARTRY
BG0
BG1 (DIRTY_OUT)
BG2 (TWE)
BG3 (DCS)
BR0
BR1 (DIRTY_IN)
BR2 (TV)
BR3 (BA0)
CI
DBG0
DBG1 (TOE)
DBG2 (DWE0)
DBG3 (DWE1)
DBGLB (CKE)
DH[0:31]
R2, P2, N2, M2, L2, K2, J5, K4, K5, K6, J2, J6, J3, J4, H3, H4, H2,
G2, F1, E1, E2, F4, E3, D1, C1, C2, B1, C3, B2, E4, D3, E5
D2
F2
K3
R4
R5
T1
L3
T3
T6
T5
N3
L5
U4
P3
H11
J10
T14, R13, R14, P13, P14, N13, U3, W1, V2, W2, V3, W3, V4, W4,
V5, W5, V6, W6, V7, W7, V8, W8, N8, W9, V9, W10, V10, W11,
V11, W12, V12, W13
U6, T7, U7, T8, U8, R8, P8, N9, P9, R9, U9, T9, U10, T10, U13,
T13, R12, N14, M13, T2, U1, U2, V1, U15, V16, U14, W16, V15,
W15, V14, W14, V13
M3
N4
J11
N1
L4
J1
R1
G3, G4, F3
G1, H1, K1, L1, M1
M4
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
I/O
I/O
I/O
Output
Output
Output
Output
Input
Input
Input
Input
I/O
Output
Output
Output
Output
Output
I/O
Active
I/O
DL[0:31]
High
I/O
GBL
LBCLAIM
MCP
TA
TBST
TEA
TS
TSIZ[0:2]
TT[0:4]
WT
Low
Low
Low
Low
Low
Low
Low
High
High
Low
I/O
Input
Output
I/O
I/O
Output
I/O
I/O
I/O
I/O
5
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