SN54HC259, SN74HC259
8 BIT ADDRESSABLE LATCHES
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current Inverting Outputs Drive Up To
D
D
D
D
D
D
D
D
D
D
10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 14 ns
±4-mA
Output Drive at 5 V
Low Input Current of 1
µA
Max
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
Asynchronous Parallel Clear
Active-High Decoder
Enable Input Simplifies Expansion
Expandable for n-Bit Applications
Four Distinct Functional Modes
SN54HC259 . . . J OR W PACKAGE
SN74HC259 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
S0
S1
S2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CLR
G
D
Q7
Q6
Q5
Q4
SN54HC259 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 40
SOIC − D
−40 C 85°C
−40°C to 85 C
SOP − NS
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
S2
Q0
NC
Q1
Q2
S1
S0
NC
V
CC
CLR
3
4
5
6
7
8
2 1 20 19
18
17
16
15
14
9 10 11 12 13
G
D
NC
Q7
Q6
NC − No internal connection
ORDERABLE
PART NUMBER
SN74HC259N
SN74HC259D
SN74HC259DR
SN74HC259DT
SN74HC259NSR
SN74HC259PWR
SN74HC259PWT
SNJ54HC259J
SNJ54HC259W
SNJ54HC259FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Q3
GND
NC
Q4
Q5
TOP-SIDE
MARKING
SN74HC259N
HC259
HC259
HC259
SNJ54HC259J
SNJ54HC259W
SNJ54HC259FK
1
SN54HC259, SN74HC259
8 BIT ADDRESSABLE LATCHES
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all
latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines
are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the
D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.
Function Tables
FUNCTION
INPUTS
CLR
H
H
L
L
G
L
H
L
H
OUTPUT OF
ADDRESSED
LATCH
D
QiO
D
L
EACH
OTHER
OUTPUT
QiO
QiO
L
L
FUNCTION
Addressable latch
Memory
8-line demultiplexer
Clear
LATCH SELECTION
SELECT INPUTS
S2
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
LATCH
ADDRESSED
0
1
2
3
4
5
6
7
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8 BIT ADDRESSABLE LATCHES
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram
S0
1
D
C
R
D
C
R
D
C
R
D
C
R
S2
3
D
C
R
D
C
R
G
14
D
C
R
D
13
D
C
R
CLR
15
Q
12
Q7
Q
11
Q6
Q
9
4
Q
Q0
Q
5
Q1
S1
2
Q
6
Q2
Q
7
Q3
Q4
Q
10
Q5
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
3
SN54HC259, SN74HC259
8 BIT ADDRESSABLE LATCHES
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram, each internal latch (positive logic)
C
D
C
C
TG
Q
C
C
C
TG
R
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC259
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC259
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8 BIT ADDRESSABLE LATCHES
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
SN54HC259
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC259
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
nA
µA
pF
V
V
MAX
UNIT
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
2V
CLR low
tw
Pulse duration
G low
4.5 V
6V
2V
4.5 V
6V
2V
tsu
Setup time, data or address before G↑
4.5 V
6V
2V
th
Hold time, data or address after G↑
G
4.5 V
6V
TA = 25°C
MIN
MAX
80
16
14
80
16
14
75
15
13
5
5
5
SN54HC259
MIN
120
24
20
120
24
20
115
23
20
5
5
5
MAX
SN74HC259
MIN
100
20
17
100
20
17
95
19
16
5
5
5
ns
ns
ns
MAX
UNIT
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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