Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[3]
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
Automatic CE
Power-Down
Current
GND < V
I
< V
CC
GND < V
I
< V
CC
Output Disabled
V
CC
= Max. I
OUT
= 0 mA
Max. V
CC
, CE > V
IH,
Min. Duty Cycle = 100%
Max. V
CC
, CE
1
>V
CC
–0.3V,
V
IN
> V
CC
–0.3V
or V
IN
< 0.3V
Test Conditions
V
CC
= Min., I
OH =
–4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
120
40
2.2
–0.5
–10
–10
Max.
Min.
2.4
0.4
V
CC
0.8
+10
+10
120
40
2.2
–0.5
–10
–10
-20
Max.
-35, -45
Min.
2.4
0.4
V
CC
0.8
+10
+10
120
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
40
20
20
mA
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. V
IL
(min.) = –3.0V for pulse durations less than 30 ns.
Document #: 38-05028 Rev. *A
Page 2 of 9
CY7C128A
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
R1 481Ω
5V
OUTPUT
GND
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
R1 481Ω
3.0V
10%
ALL INPUT PULSES
90%
90%
10%
≤
5 ns
C128A–5
≤
5 ns
(a)
(b)
C128A–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
Over the Operating Range
[2, 5]
-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6]
WE HIGH to Low Z
5
15
12
12
0
0
12
10
0
7
5
0
15
20
15
15
0
0
15
10
0
7
5
5
8
0
20
25
25
25
0
0
20
15
0
10
5
3
8
5
8
0
20
40
30
30
0
0
20
15
0
15
5
15
10
3
8
5
15
0
25
15
15
5
20
10
3
12
5
15
20
20
5
35
15
3
15
35
35
5
45
20
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-20
Max.
Min.
-35
Max.
Min.
-45
Max.
Unit
WRITE CYCLE
[8]
Notes:
4. Tested initially and after any design or process changes that may affect these parameters
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05028 Rev. *A
Page 3 of 9
CY7C128A
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C128A–6
Read Cycle No. 2
[9, 11]
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
PD
I
CC
50%
I
SB
C128A–7
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[8]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
C128A–8
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected. OE, CE = V
IL
.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05028 Rev. *A
Page 4 of 9
CY7C128A
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[8, 12, 13]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
C128A–9
t
SCE
t
HA
t
HD
Notes:
12. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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