TDA8025
IC card interface
Rev. 01 — 6 April 2009
Product data sheet
1. General description
The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating
at 3 V, 1.8 V or optionally, 1.2 V. Using few external components, the TDA8025 provides
integrated supply, protection and control functions for a range of applications.
2. Features
I
I
I
I
I
Integrated circuit smart card interface
3 V, 1.8 V or 1.2 V smart card supply
Low power consumption in inactive mode
Three protected, half duplex, bidirectional buffered input/output lines (C4, C7 and C8)
V
CC
regulation:
N
3 V, 1.8 V or optionally 1.2 V at
±
5 % using one 220 nF and one 470 nF low ESR
multilayer ceramic capacitor.
N
Current pulse handling for pulses of 40 nAs at V
CC
= 3 V, 15 nAs at V
CC
= 1.8 V or
V
CC
= 1.2 V up to 20 MHz
Thermal and short-circuit protection for all card contacts
Automatic activation and deactivation sequences triggered by short-circuit, card
take-off, overheating, falling V
DD(INTF)
and V
DD(INTREGD)
Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV
Clock signal using the internal oscillator or an external crystal (≤ 26 MHz) connected to
pin XTAL1
Card clock generation up to 20 MHz with synchronous frequency changes of f
xtal
,
1
⁄
f
1
1
2 xtal
,
⁄
4
f
xtal
or
⁄
8
f
xtal
using pins CLKDIV1 and CLKDIV2
Non-inverted control of pin RST using pin RSTIN
NDS certified
Supply supervisors during power on and off:
N
V
DD(INTREGD)
using a fixed threshold
N
V
DD(INTF)
using resistor bridge threshold adjustment
Built-in debouncing on card presence contacts (typically 4.5 ms)
Multiplexed status signal using pin OFFN
I
I
I
I
I
I
I
I
I
I
3. Applications
I
I
I
I
Pay TV
Electronic payment
Identification
Bank card readers
NXP Semiconductors
TDA8025
IC card interface
Table 1.
Symbol
I
CC
Quick reference data
…continued
Parameter
supply current
Conditions
0 V to 3 V
0 V to 1.8 V
0 V to 1.2 V
Min
-
-
-
0.02
[2]
Typ
-
-
-
0.14
80
-
-
Max
65
65
30
0.26
100
0.56
+85
Unit
mA
mA
mA
V/µs
µs
W
°C
SR
General
t
deact
P
tot
T
amb
[1]
slew rate
deactivation time
total power
dissipation
ambient temperature
up or down
total sequence
T
amb
=
−25 °C
to +85
°C
35
-
−25
To enable the microcontroller to provide the required maximum voltage input level on XTAL1, V
DD(INTF)
must not exceed
V
DD(INTREGD)
+ 0.3 V. See
Section 8.1 on page 7
for specific limitations on the maximum V
DD(INTF)
voltage and
Table 8 on page 23
for
the limits of XTAL1.
See
Figure 12 on page 18.
[2]
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA8025HN
HVQFN32
Description
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT617-1
Type number
TDA8025_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 April 2009
3 of 38
NXP Semiconductors
TDA8025
IC card interface
7. Pinning information
7.1 Pinning
26 ENCLKIN
31 AUX2UC
30 AUX1UC
25 PORADJ
24 TEST3
23 OFFN
22 RSTIN
21 V
DDI(REG)
20 GND
19 V
DD(INTREGD)
18 V
CC
17 RST
PRES 10
I/O 11
AUX2 12
AUX1 13
CGND 14
CLK 15
CONFIG 16
9
001aai958
32 TEST4
28 XTAL1
terminal 1
index area
CMDVCCN
TEST1
TEST2
V
DD(INTF)
CLKDIV2
CLKDIV1
VCC_SEL1
VCC_SEL2
1
2
3
4
5
6
7
8
TDA8025
PRESN
Transparent top view
Fig 2.
Pin configuration (HVQFN32)
7.2 Pin description
Table 3.
Symbol
CMDVCCN
TEST1
TEST2
V
DD(INTF)
CLKDIV2
CLKDIV1
VCC_SEL1
Pin description
Pin Type
[1]
Description
1
2
3
4
5
6
7
I
I
I
P
I
I
I
microcontroller start activation sequence input; active LOW
test pin; connect to GND
test pin; connect to GND
interface supply voltage
sets the clock frequency; used together with pin CLKDIV1;
see
Table 4 on page 12
sets the clock frequency; used together pin CLKDIV2; see
Table 4 on
page 12
optional 1.2 V selection control signal:
active HIGH: V
CC
= 1.2 V
active LOW: disables 1.2 V selection
VCC_SEL2
8
I
3 V or 1.8 V selection control signal:
active LOW: V
CC
= 3 V
active HIGH: V
CC
= 1.8 V when pin VCC_SEL1 is active LOW
PRESN
PRES
I/O
AUX2
AUX1
TDA8025_1
9
10
11
12
13
I
I
I/O
I/O
I/O
card presence contact input; active LOW
[2]
card presence contact input; active HIGH
[2]
card input/output data line (C7)
[3]
card auxiliary 2 input/output data line (C8)
[3]
card auxiliary 1 input/output data line (C4)
[3]
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 April 2009
27 XTAL2
29 I/OUC
5 of 38
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