140 – 155 Mbit/s
CMI Encoder/
Decoder
GD16367B/GD16368B
Preliminary
General Description
The GD16367B and GD16368B is a
chip- set intended for use in SDH STM-1/
SONET OC-3 and PDH E4 systems,
where electrical CMI coded interface is
needed.
The chip set is designed to take care of
all processing above 78 MHz in an
STM-1/OC-3/E4 interface, accommodat-
ing both electrical (CMI) and optical
(NRZ) data format. Hence the same
board may be configured as STM-1o,
STM-1e, E4o, or E4e at system integra-
tion level.
encoder may be switched off when the
interface is optical.
Features
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Integrates all high-speed signal
processing above 78 MHz.
ITU-T G.703 CMI encoding/decoding
for STM-1 and E4 electrical inter-
faces.
Meet G.751, G.823 and G.825 for
jitter tolerance and jitter generation.
Remote and local loops available.
CMI disable function for board level
configuration for optical interface.
Selectable 2, 4 or 8 bit parallel inter-
face for maximum flexibility.
Selectable 0°, 90°, 180°, 270° phase
relation for parallel data I/O.
3.3 V LVPECL High speed I/O’s.
CMOS Interface to system ASIC.
Power consumption typical:
– 400 mW for GD16367B
– 600 mW for GD16368B
3.3 V supply; 5 V for VCO.
Designed for low cost and volume
production.
High-speed BiCMOS technology.
Package 52 pin PQFP (10 x 10 mm).
The Decoder - GD16368B
The DeMUX/Decoder device provides
clock and data recovery extracting the
280/311 MHz clock of the incoming CMI
signal and a decoder that turns CMI to
NRZ. CMI code violations are detected
and signaled by the CODV output. The
CMI decoder may be switched off when
the interface is optical
Both devices provide selectable 2, 4 or
8 bit parallel interface to the processing
device for maximum flexibility.
The phase relation between parallel data
and clock is selectable in four phases
(0°, 90°, 180°, 270°) providing flexible
timing between the system and the
devices.
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The Encoder - GD16367B
The MUX/Encoder device generates the
CMI coded data signal and associated
clock at 280/311 MHz. The reference in-
put clock for the clock synthesis may be
selected from two individual inputs, 70/
78 MHz or 17/19 MHz allowing for pro-
grammable selection between reference
inputs for E4 or STM-1/OC-3. The CMI
SEL1
SIP
SIN
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SEL2
SEL3
PW1
PW2
SLB
LLB
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CMI / NRZ
DOU0
GD16368B
SLSIN
SLSIP
CKRF LLSOP LLSON LLCOP LLCON
DOU7
DOCK
CODV
2 / 4 / 8 bit NRZ
17 - 78 MHz
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STM-1 Processing ASIC
Line Interface Unit
CMI / NRZ
280 / 311 MHz
140 / 151 MHz
CKRU
LLSIP
LLSIN
LLCIP LLCIN
Applications
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SLSOP
SLSON
SOP
SON
CKO
CKN
DIN0
GD16367B
DIN7
DICK
2 / 4 / 8 bit NRZ
17 - 78 MHz
Tele Communication:
– SDH STM-1
– SONET OC-3
– PDH E4
Data Sheet Rev. 14
STM-1
F4
VCO
LPF
PDH-REF
STM-REF
LLB
SLB
PW1
PW2
ICV
SEL1
SEL2
SEL3
SEL4
Functional Details, Both Devices
General
The GD16367B/GD16368B chip set pro-
vides transmission of 140 Mbit/s (E4) and
155 Mbit/s (STM-1/OC-3).
Both Optical NRZ signal transmission
and Electrical CMI-coded signal trans-
mission are supported by the internal
selectable CMI-Encoding/Decoding
circuitry.
Selectable 2/4/8 bit system interface is
provided.
Line/System Loop Back
Connecting the differential Line Loop sig-
nals and clocks (LLxxx) from GD16368B
to GD16367B allows loop-back of the re-
ceived and recovered line signal, when
LLB is high on both devices. The Line
Loop back is also called remote loop
back.
Connecting the differential System Loop
signals (SLxxx) from GD16367B to
GD16368B allows system loop back,
when SLB is high on both devices. The
System Loop back is also called a local
loop back.
140/155 Mbit/s and NRZ/CMI
Clock Frequencies
The VCO tuning range covers the clock
frequencies of 280 MHz to 311 MHz. The
actual clock frequency is determined by
reference clocks and received data.
The 280/311 MHz are used for CMI-oper-
ation. When operating in NRZ-mode the
VCO clock is divided by 2.
Loop Filters
Both circuits comprise fully integrated
PLL functions for re-timing data at the
transmit site, and for clock and data re-
covery at the receive site.
A passive loop filter consisting of a resis-
tor and a capacitor is used for each de-
vice. The external loop filters are
terminated to VEEA as shown in
Figure 1
(for the transmitter) and
Figure 4
(for the
receiver).
The loop filter values are optimised at the
evaluation board GD90367/368. The op-
timal values depend on the actual appli-
cation. The suggested values in
Figures
1
and
4
can be used as starting point for
the optimisation.
NRZ/CMI and Parallel Width
Selection
The devices can operate in different line
and system modes; selected by SEL1,
PW2, and PW1 (See Table 1).
The bit order at the system site is defined
with bit 0 as the first bit transferred (DIN0
for the transmitter and DOU0 for the re-
ceiver).
Mode
CMI, 2 bit
CMI, 4 bit
CMI, 8 bit
Not valid
NRZ, 2 bit
NRZ, 4 bit
NRZ, 8 bit
Not valid
Table 1
SEL1
0
0
0
0
1
1
1
1
PW2
0
0
1
1
0
0
1
1
PW1
0
1
0
1
0
1
0
1
Line Clock
[Frequency/MHz]
280/311
280/311
280/311
-
140/155
140/155
140/155
-
System Clock
[Frequency/MHz]
70/78
35/39
17/19
-
70/78
35/39
17/19
-
Used Bits
0&1
0...3
0...8
-
0&1
0...3
0...8
-
NRZ/CMI and parallel width selection. This table is common for both devices.
Data Sheet Rev. 14
GD16367B/GD16368B
Page 2 of 14
Functional Details, The Transmitter - GD16367B
The GD16367B is the encoder/transmit-
ter (see
Figure 1)
with:
u
Multiplexer (2/4/8:1)
u
Selectable CMI-Encoding
u
NRZ/CMI data and clock differential
outputs
u
Selectable System Loop Back data
differential output
u
Selectable Line Loop Back data and
clock differential inputs
Counter Clocking
The output clock (DICK) is used for
clocking out the parallel system data into
the MUX. The frequency of DICK de-
pends on the reference clock and the
multiplexing mode (See Table 1 on
page
2).
Four phases timing relation between
DINx and DICK are provided by the
SEL2 and SEL3 (See AC Characteristics
on
page 11,
and Pin List on
page 7).
and a 280/311 MHz clock (CKO/CKN)
from the CMI-encoder. See the CMI-
coding in Table 2.
NRZ:
0
CMI:
01
Note:
consecutive NRZ zeros
“0000..” gives
“01010101...” as
CMI-output
Multiplexer
The parallel input data (DIN0...DIN7) are
received by the multiplexer. This is done
synchronously with the DICK output
clock, which is used when counter clock-
ing. Counter clocking allows 2:1, 4:1 ,
and 8:1 multiplexing. Forward clocking is
only possible when operating in the 2:1
mode.
A low noise reference clock is recom-
mended, as the clock noise within the
PLL loop bandwidth is transmitted as jit-
ter on the serial outputs. The 70/78 MHz
clock input (CKR0) is selected when
SEL4 is low. The 17/19 MHz clock input
(CKR1) is selected when SEL4 is high.
For PDH system rates 17 or 70 MHz is
used. For SDH system rates 19 or
78 MHz is used.
Forward Clocking
When operated in 2:1 multiplexing mode,
a forward clocking scheme can be used:
u
Set PW1=PW2=SEL4=0
u
Connect the forwarded 70/78 MHz
clock to CKR0.
The control inputs (SEL2 and SEL3) con-
trol the timing relation between DINx and
CKR0, see pin list on
page 7.
1
00/11 consecutive NRZ ones
“1111...” gives
“00110011...” as
CMI-output
CMI Coding.
Table 2
CMI-Encoder
When the CMI-encoding is enabled
(SEL1=0), every bit of the 140/155 Mbit/s
output from the multiplexer is encoded to
a 2-bit CMI-word, resulting in a 280/
311 Mbit/s output of the CMI-encoder;
When the CMI-encoding is disabled
(SEL1=1), the 140/155 Mbit/s output from
the multiplexer is passed through the
CMI-encoder; and a 140/155 MHz clock
(CKO/CKN) is generated from the
CMI-encoder.
LLSIN
LLSIP
LLCIN
LLCIP
SEL1
ICV
PW2
PW1
SLB
LLB
VEE
TCK
SELTCK
DIN0
MUX
DIN7
VDD
VDDA
SLSOP
SLSON
SOP
SON
CKR0
CKR1
SEL2
SEL3
SEL4
Clock
Synth.
CMI
Encoder
CKO
CKN
CKRU
DICK
Figure 1.
Block Diagram - GD16367B
VEEA
Data Sheet Rev. 14
CLOF
680Ω
2.2
µ
F
GD16367B/GD16368B
Page 3 of 14
Outputs
The outputs from the multiplexer are fed
to the LVPECL output stages.
See
Figures 2
and
3
for output termina-
tion.
The serial data output (SOP/SON) is ac-
companied by a differential clock output
(CKO/CKN). See AC Characteristics on
page 11.
SLSOP/SLSON is enabled when SLB is
high. When SLB is low SLSOP=0 and
SLSON=1; thus avoiding noise injection
at normal operation.
The clock output (CKRU) provides a
70/78 MHz clock suitable for driving the
GD16368B receiver (connect to CKRF
input).
Output
LVPECL
100nF
Input
LVPECL
100nF
180Ω
0V
(GND)
180Ω
50Ω
50Ω
2V
(VCC -1.3V)
e.g. GD16360
Figure 2.
LVPECL Output Termination, AC-coupled.
Output
LVPECL
Input
LVPECL
50Ω
50Ω
1.3V
(VCC -2V)
e.g. GD16360
Figure 3.
LVPECL Output Termination, DC-coupled.
Data Sheet Rev. 14
GD16367B/GD16368B
Page 4 of 14
Functional Details, The Receiver - GD16368B
The GD16368B is the receiver (see
Figure 4)
with:
u
Clock&Data Recovery (CDR)
u
Selectable CMI-Decoding
u
Demultiplexer (1:2/4/8)
u
Selectable System Loop Back data
differential input
u
Selectable Line Loop Back / 1:1 CDR
data and clock outputs
CMI-Decoder
When the CMI-decoding is enabled
(SEL1=0), 280/311 Mbit/s is decoded as
2-bits CMI-words into 1-bit NRZ 140/
155 Mbit/s. The internal 140/155 MHz
clock is aligned to the CMI-words. See
Table 2 on
page 3
for the CMI-coding.
When the CMI-decoding is disabled
(SEL1=1), the 140/155 Mbit/s data signal
is passed unchanged through the CMI-
decoder.
Inputs
The serial input is selected by SLB. For
normal operation, SIP/SIN is selected
when SLB is low. For system loop back
operation, SLSIP/SLSIN is selected
when SLB is high.
The selected serial input data is the input
of the CDR, where the clock and data is
recovered.
The PLL constantly attempts to lock to
the incoming data stream. In case the in-
coming data signal is lost, the VCO will
drift away from the CKRF reference fre-
quency. The VCO is monitored by a
built-in lock detector. When it drifts more
than 500 ppm (or 2000 ppm, selectable)
away from the reference frequency, it is
“kicked back” to the reference frequency
and starts hunting for incoming data
again.
CKRF does not have any part in the jitter
performance (as long as the incoming
data frequency is within 500 ppm of the
required 70/78 MHz).
Outputs
The 140/155 Mbit/s recovered (and de-
coded) data is de-multiplexed into 2, 4, or
8 parallel data bits (DOU0...DOU7) se-
lected by PW1 and PW2 (see Table 1 on
page 2).
DOCK is the output clock synchronous to
the parallel data (See AC Characteristics
on
page 11
).
The phase can be adjusted with SEL2
and SEL3 (0°/90°/180°/270°, see pin list).
If the incoming data stream is lost, DOCK
will be floating within a +/-500(2000) ppm
window around the CKRF frequency (di-
vided by 1, 2, or 4 depending of the par-
allel bit rate). In CMI-mode, the CODV
output will be signalling errors if the sig-
nal is lost.
20Ω
1
µ
F
CKRF
VEEA
CLOF
SEL1
SEL2
SEL3
PW1
PW2
TCK
SELTCK
SIP
SIN
SLSIP
SLSIN
SLB
DOU0
CDR
CMI
Decoder
De-
MUX
DOU7
DOCK
CODV
LLB
LDS1
LDS2
LLSOP
LLSON
LLCOP
LLCON
VEE
VDD
VDDA
Figure 4.
Block Diagram - GD16368B
Data Sheet Rev. 14
GD16367B/GD16368B
Page 5 of 14
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