Datasheet> 器件分类 > 存储> 存储> CY7C1061G30-10BVJXI

CY7C1061G30-10BVJXI: 产品描述Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, VFBGA-48; 产品类别存储存储; 文件大小578KB，共25页; 制造商Cypress(赛普拉斯); 标准

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CY7C1061G30-10BVJXI在线购买

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CY7C1061G30-10BVJXI概述

Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, VFBGA-48

CY7C1061G30-10BVJXI规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	VFBGA,
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	10 ns
JESD-30 代码	R-PBGA-B48
长度	8 mm
内存密度	16777216 bit
内存集成电路类型	STANDARD SRAM
内存宽度	16
功能数量	1
端子数量	48
字数	1048576 words
字数代码	1000000
工作模式	ASYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	1MX16
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL
座面最大高度	1 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	2.2 V
标称供电电压 (Vsup)	3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	0.75 mm
端子位置	BOTTOM
宽度	6 mm
Base Number Matches	1

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CY7C1061G/CY7C1061GE

16-Mbit (1M words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (1M words × 16 bit) Static RAM with Error-Correcting Code (ECC)

Features

■

High speed

❐

= 10 ns/15 ns

Embedded error-correcting code (ECC) for single-bit error

correction

Low active and standby currents

❐

= 90 mA typical at 100 MHz

❐

SB2

= 20 mA typical

Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and

4.5 V to 5.5 V

1.0 V data retention

Transistor-transistor logic (TTL) compatible inputs and outputs

Error indication (ERR) pin to indicate 1-bit error detection and

correction

Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball

VFBGA packages

To access devices with a single chip enable input, assert the chip

enable (CE) input LOW. To access dual chip enable devices,

assert both chip enable inputs – CE

as LOW and CE

as HIGH.

To perform data writes, assert the Write Enable (WE) input LOW,

and provide the data and address on the device data pins (I/O

through I/O

) and address pins (A

through A

) respectively.

The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs

control byte writes, and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O

through

I/O

and BLE controls I/O

through I/O

To perform data reads, assert the Output Enable (OE) input and

provide the required address on the address lines. Read data is

accessible on I/O lines (I/O

through I/O

). You can perform

byte accesses by asserting the required byte enable signal (BHE

or BLE) to read either the upper byte or the lower byte of data

from the specified address location.

All I/Os (I/O

through I/O

) are placed in a high-impedance state

when the device is deselected (CE HIGH for a single chip enable

device and CE

HIGH / CE

LOW for a dual chip enable device),

or control signals are de-asserted (OE, BLE, BHE).

On the CY7C1061GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = High). See the

Truth Table

on page 16

for a complete description of read and write modes.

The logic block diagrams are on page 2.

The CY7C1061G and CY7C1061GE devices are available in

48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.

For a complete list of related documentation, click

here.

■

Functional Description

CY7C1061G and CY7C1061GE are high-performance CMOS

fast static RAM devices with embedded ECC

[1]

. Both devices are

offered in single and dual chip enable options and in multiple pin

configurations. The CY7C1061GE device includes an ERR pin

that signals a single-bit error-detection and correction event

during a read cycle.

Product Portfolio

Current Consumption

Product

Features and Options

(see

Pin Configurations on

page 4)

Single or dual chip enables

Optional ERR pins

Address MSB A

placement options

compatible with Cypress and

other vendors

Range

(V)

1.65 V–2.2 V

2.2 V–3.6 V

4.5 V–5.5 V

Speed Operating I

, (mA)

(ns)

f = f

max

10/15

Typ

[2]

Max

110

Standby, I

SB2

(mA)

Typ

[2]

Max

CY7C1061G18

CY7C1061G(E)30

CY7C1061G

Industrial

Notes

1. This device does not support automatic write-back on error detection.

2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V

= 1.8 V (for a V

range of 1.65 V–2.2 V),

= 3 V (for a V

range of 2.2 V–3.6 V), and V

= 5 V (for a V

range of 4.5 V–5.5 V), T

= 25 °C.

Cypress Semiconductor Corporation

Document Number: 001-81540 Rev. *S

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 16, 2017

CY7C1061G30-10BVJXI

CY7C1061G30-10BVJXI在线购买

CY7C1061G30-10BVJXI概述

CY7C1061G30-10BVJXI规格参数

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