into the location specified on the address pins (A
0
through
A
18
). Likewise, B
C
and B
D
correspond with the I/O pins I/O
16
to I/O
23
and I/O
24
to I/O
31
, respectively.
Reading from the device is accomplished by enabling the chip
(CE
1,
CE
2
, and CE
3
LOW) while forcing the Output Enable
(OE) LOW and Write Enable (WE) HIGH. If the first Byte
Enable (B
A
) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
Enable B (B
B
) is LOW, then data from memory will appear on
I/O
8
to I/O
15
. Similarly, B
c
and B
D
correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O
0
through I/O
31
) are placed in a
high-impedance state when the device is deselected (CE
1,
CE
2
or CE
3
HIGH), the outputs are disabled (OE HIGH), the
byte selects are disabled (B
A-D
HIGH), or during a write
operation (CE
1,
CE
2
, and CE
3
LOW, and WE LOW).
The CY7C1062AV25 is available in a 119-ball pitch ball grid
array (PBGA) package.
WE
CE
1
CE
2
CE
3
OE
B
A
B
B
B
C
B
D
I/O
0
–I/O
31
Functional Description
The CY7C1062AV25 is a high-performance CMOS Static
RAM organized as 524,288 words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE
1,
CE
2
and CE
3
LOW) and forcing the Write Enable (WE)
input LOW. If Byte Enable A (B
A
) is LOW, then data from I/O
pins (I/O
0
through I/O
7
), is written into the location specified on
Logic Block Diagram
INPUT BUFFERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
512K x 32
ARRAY
4096 x 4096
COLUMN
DECODER
Selection Guide
-8
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Com’l
Ind’l
Com’l/Ind’l
8
300
300
50
-10
10
275
275
50
-12
12
260
260
50
mA
Unit
ns
mA
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
OUTPUT BUFFERS
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05333 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 27, 2003
CONTROL LOGIC
PRELIMINARY
Pin Configuration
119-ball PBGA
(Top View)
CY7C1062AV25
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
NC
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
2
A
A
B
c
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
A
A
A
3
A
A
CE
2
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
B
d
A
A
4
A
CE
1
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
WE
OE
5
A
A
CE
3
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
B
b
A
A
6
A
A
B
a
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
A
A
A
7
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
DNU
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
Document #: 38-05333 Rev. **
Page 2 of 9
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
CY7C1062AV25
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
2.5V
±
0.2V
.... –0.5V to +3.6V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Electrical Characteristics
Over the Operating Range
-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output
Disabled
V
CC
= Max., f = f
MAX
Com’l
= 1/t
RC
Ind’l
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V,
or V
IN
< 0.2V, f = 0
Com’l/Ind’l
Test Conditions
V
CC
= Min.,
I
OH
= –1.0mA
V
CC
= Min.,
I
OL
= 1.0 mA
2.0
–0.3
–1
–1
Min.
2.0
0.4
V
CC
+ 0.3
0.8
+1
+1
300
300
100
2.0
–0.3
–1
–1
Max.
2.0
0.4
V
CC
+ 0.3
0.8
+1
+1
275
275
100
2.0
–0.3
–1
–1
-10
Min.
Max.
2.0
0.4
V
CC
+ 0.3
0.8
+1
+1
260
260
100
-12
Min.
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB2
50
50
50
mA
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 2.5V
Max.
8
10
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05333 Rev. **
Page 3 of 9
PRELIMINARY
AC Test Loads and Waveforms
[3]
50Ω
OUTPUT
Z
0
= 50Ω
V
TH
= V
DD
/2
30 pF
Including all Components
R1 317Ω of Test Equipment
2.5V
90%
GND
Rise time > 1 V/ns
10%
CY7C1062AV25
ALL INPUT PULSES
90%
10%
Fall time:
> 1 V/ns
1.73V
(a)
2.5V
Including OUTPUT
Jig and
Scope
5 pF
(b)
R2
351Ω
[4]
THÉVENIN EQUIVALENT
167Ω
OUTPUT
(c)
-8
-10
Max.
Min.
1
10
8
3
8
5
1
5
Low-Z
[6]
3
5
0
8
5
1
5
8
6
6
0
0
6
5
0
3
10
7
7
0
0
7
5.5
0
3
1
5
12
8
8
0
0
8
6
0
3
0
10
5
1
6
3
5
0
12
6
1
5
3
6
3
10
5
1
6
10
3
12
6
Max.
-12
Min.
1
12
12
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
V
CC
(typical) to the first access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
, CE
2
, or CE
3
LOW to Data Valid
OE LOW to Data Valid
OE LOW to
Low-Z
[6]
[6]
Description
Min.
1
8
OE HIGH to High-Z
CE
1
, CE
2
, or CE
3
LOW to
CE
1
, CE
2
, or CE
3
HIGH to High-Z
[6]
CE
1
, CE
2
, or CE
3
LOW to Power-up
[7]
CE
1
, CE
2
, or CE
3
HIGH to Power-down
[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
Cycle
[8, 9]
Write Cycle Time
CE
1
, CE
2
, or CE
3
LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[6]
[6]
[6]
Byte Disable to High-Z
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(2.3V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 1.5V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. t
power
time has to be provided initially before a read/write operation is
started.
6. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
, and t
LZOE
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05333 Rev. **
Page 4 of 9
PRELIMINARY
AC Switching Characteristics
Over the Operating Range
[4]
(continued)
-8
Parameter
t
HZWE
t
BW
Description
WE LOW to High-Z
[6]
Byte Enable to End of Write
6
Min.
Max.
5
7
-10
Min.
Max.
5
CY7C1062AV25
-12
Min.
8
Max.
6
Unit
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
2.3V
t
CDR
CE
V
DR
> 1.5V
2.3V
t
R
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[11, 12]
ADDRESS
t
RC
CE
1
, CE
3
CE
2
t
ACE
OE
t
DOE
B
A
, B
B
, B
C
, B
D
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
I
SB
IICC
CC
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
10. Device is continuously selected. OE, CE, B
A
, B
B
, B
C
, B
D
= V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
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