an Intel company
2.5 Gbit/s
16:1 Multiplexer
GD16523
General Information
The GD16523 is a multirate (STM 1/4/16
plus 1.25 Gbit/s bit-rates) 16:1 re-timing
multiplexer with jitter clean-up capability.
The data inputs are forward clocked into
a 2 bit elastic buffer enabling a very low
jitter transfer by using a double PLL sys-
tem.
The GD16523 tolerates up to 1.7 UI
PP
(155 MHz) jitter on the input data and for-
ward clock relative to the jitter output
clock.
Each of the PLLs has a separate
PCMOS lock- detect output.
The VCXO reference clock input is differ-
ential and the frequency is selectable
78 MHz or 155 MHz.
Data inputs are differential LVPECL in-
puts. 2.5 GHz clock and data outputs are
differential CML with internal 50
W
termi-
nations.
The GD16523 operates from a single
+3.3 V supply voltage using 800 mW
(typical).
The GD16523 is available in a 100 pin
TQFP package (14 × 14 mm) with a heat
slug on bottom surface.
Features
l
Multirate Multiplexer:
– 2.4 - 2.7 Gbit/s
– 1.25 Gbit/s
– 622 Mbit/s
– 155 Mbit/s
Forward clocked input data.
Jitter clean-up PLL.
2 bit elastic buffer.
Differential reference clock input.
High-speed clock output.
LVTTL lock detect outputs.
Near-end loop-back output with
power down capability.
Single power supply: +3.3 V.
Power dissipation: 800 mW (typ.).
Available in a 100 pin TQFP package
(14 × 14 mm) with exposed heat slug
on bottom surface.
l
l
l
l
l
l
l
VBB
VBBS
LSEL
SLBOP
SLBON
l
DIP0
DIN0
DIP15
DIN15
DCLKP
DCLKN
16
16
Elastic
Buffer
F
W
F/2
F/2
R
F
16:1
MUX
DOUTP
DOUTN
l
l
/2
Narrow
band
LPF
CHAP1
CKOP
CKON
PFD1
/2
Clock
Generator
BRS0
BRS1
NLOCK1
NLDC1
CSEL
NLOCK2
VCXIP
VCXIN
75 - 85 MHz
150 - 169 MHz
PFD2
VCO
2.4-2.7 GHz
CHAP2
XSEL
SLTCK TCK
VCTL
NLDC2
VEE
VEEA
VCC
VCCA
VCXO
Wideband
LPF
Data Sheet Rev.: 16
Functional Details
The GD16523 multiplexes the 16 data in-
puts (DIP/N0-15) into a single data out-
put (DOUT) with DIP/N0 as the first bit to
be output and DIP/N15 as the last. The
data inputs are forward clocked by the
DCLK input. The data inputs are differen-
tial LVPECL type and the output is differ-
ential CML, driving 10 mA in a 50
W
load
connected to VCC.
In order to reduce jitter on the data out-
put a 2 bit elastic buffer combined with a
double PLL system has been imple-
mented. The first PLL consists of an ex-
ternal passive loop filter and an external
crystal VCO (VCXO). The centre fre-
quency of the external VCXO can be
selected to be in either range 150 -
169 MHz or 75 - 85 MHz by the XSEL
pin. The second PLL requires only a pas-
sive external loop filter consisting of a re-
sistor and a capacitor.
The jitter performance on the output of
the chip depends on three phase noise
contributing sources: the forward clock
(DCLK), the external VCO (VCXO) and
the internal VCO, see
Figure 1.
The out-
put noise is a combination of these three
curves. First the noise follows the DCLK
curve until the loop-bandwidth of LPF1
then the noise follows the curve of the
VCXO until the loop-bandwidth of LPF2,
and finally it follows the noise of the inter-
nal VCO, see
Figure 2.
Above the PLL1 loop-filter frequency the
noise performance is determined by the
VCXO therefore the PLL1 loop-filter fre-
quency should be set as low as possible.
At the same time the jitter difference be-
tween the forward clock and output clock
may not exceed 1.7 UI
PP
(155 MHz). The
optimum bandwidth of PLL1 is therefore
the bandwidth where just below 1.7 UI
PP
of jitter is filtered away from the forward
clock.
The optimum loop bandwidth of PLL2 is
the frequency where the VCO curve
crosses the VCXO curve, see
Figure 1.
A no-lock detect output pin is available
for each PLL, indicating if the corre-
sponding PLL is out of lock. To enable
this function a 5 - 10 nF capacitor should
be connected to each of the NLDC pins.
This capacitor filters the NLDET signal
generated internally by XORing the two
signals going to the PFD and putting this
through a charge pump to the NLDC pin.
This filtering enables the NLOCK pin to
go low when the corresponding PLL is in
lock and high when out of lock.
A high level on the CSEL input bypasses
the PLL1 so that the write signal to the
elastic buffer goes directly to the PFD2. It
also bypasses the divider between the
Clock Generator and the PFD2. Note that
changing the bit rate in this mode
changes the loop-bandwidth of PLL2.
The auxillary output SLBOP/SLBON is a
second data output to accommodate
near-end loop back. To save power in
normal operation and reduce noise in the
receiver the output can be turned off by
setting LSEL low.
The two bit rate select signals BRS1 and
BRS0 select the bit rate of the chip.
BRS1
1
1
0
0
BRS0
1
0
1
0
DIP/N0..15
155 Mbit/s
77 Mbit/s
38 Mbit/s
9.7 Mbit/s
DOUTP/N
2.5 Gbit/s
1.25 Gbit/s
622 Mbit/s
155 Mbit/s
Application Details
PLL Loop Filters
The loop filters can be made as shown in
Figure 3.
For optimal jitter performance
the values of LPF1 should be adjusted
according to the jitter on the input data
and the values for LPF2 should be ad-
justed according to the jitter on the
VCXO.
CHAP1
8k2
1u
VCC
PFD1
VCXIP
VCXIN
PFD2
VCO
VCXO
CHAP2
3k3
100n
VCCA
VCTL
Figure 3.
Loop Filters
For noise and jitter reasons it is important
that the capacitor (C2) is connected to
VCCA close to the VCTL pin.
Signal Power
From
DCLK
From
VCXO
From
VCO
Frequency
Biasing the Data Inputs
All the data inputs are biased internally
on the chip with the 5 kW resistive net-
work to VBB as shown in
Figure 4 .
The data inputs can be used both differ-
ential and single-ended without any ex-
ternal pull-ups/downs and can be
AC-coupled as well.
The VBB input may be shorted to the
VBBS output and de-copled with at least
one external capacitor on either pin 23 or
61.
Figure 1.
Noise sources contributing to
the output noise. Normalized
to same signal power and
carrier frequency.
Signal Power
LBW1
LBW2
Frequency
DIP0
DIN0
5kW
VBB
5kW
DIP15
DIN15
5kW
5kW
Figure 2.
Spectrum of output clock, with
optimized LBW2.
Figure 4.
Data Inputs
Data Sheet Rev.: 16
GD16523
Page 2 of 10
Pin List
Mnemonic:
DIP0
DIP1
DIP2
DIP3
DIP4
DIP5
DIP6
DIP7
DIP8
DIP9
DIP10
DIP11
DIP12
DIP13
DIP14
DIP15
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
Pin numbers:
26, 27
28, 29
30, 31
32, 33
34, 35
36, 37
39, 40
41, 42
43, 44
45, 46
47, 48
49, 50
53, 54
55, 56
57, 58
59, 60
63, 64
88, 89
96
71
Pin Type:
LVPECL IN
Description:
Differential data inputs multiplexed to the serial output starting
with DIP0, followed by DIP1, DIP2....DIP15. Pre-biased to VBB.
DCLKP, DCLKN
VCXIP, VCXIN
VCTL
CSEL
LVPECL IN
LVPECL IN
ANL IN
LVTTL IN
Differential clock input. These pins are used to forward clock the
data inputs.
Differential VCXO clock input for PLL1.
Internal VCO frequency control input.
PLL1 bypass select signal.
0 (or NC)
PLL1 VCXO is active.
1
PLL1 is bypassed.
Loop select.
0 (or NC)
1
SLBOP/N output buffer is powered down.
SLBOP/N output buffer is powered up
LSEL
72
LVTTL IN
XSEL
73
LVTTL IN
Select input for reference clock frequency.
0
Selects 77.76 MHz VCXO
1 (or NC)
Selects 155 MHz VCXO.
Bit rate select.
BRS1
1 (or NC)
1 (or NC)
0
0
BRS0
1 (or NC)
0
1 (or NC)
0
DIP0..DIP15
155.52 Mbit/s
77.76 Mbit/s
38.88 Mbit/s
9.72 Mbit/s
DOUTP/N
2.488 Gbit/s
1.244 Gbit/s
622 Mbit/s
155 Mbit/s
BRS0, BRS1
68, 69
LVTTL IN
DOUTP, DOUTN
SLBOP, SLBON
SLTCK
9, 10
3, 4
91
CML OUT
CML OUT
LVTTL IN
Multiplexed data output. On-chip terminated, refer to
Figure 6.
Near-end loop back output. On-chip terminated, refer to
Figure 6.
Clock source select input.
0 (or NC)
Selects internal VCO
1
Selects TCK input
Test clock input. This pin is used as clock source instead of the
internal VCO when the SLTCK input pin is high.
Clock output in phase with the multiplexed data output. On-chip
terminated, refer to
Figure 6.
Charge-pump 1 output. Sinks current when VCXO is leading.
Sources current when VCXO is lagging, use positive transfer
VCXO.
Charge-pump 2 output. Sources current when internal VCO is
leading. Sinks current when internal VCO is lagging. Internal VCO
is negative transfer.
Reference voltage input for differential data inputs.
Reference voltage output.
PLL1 lock detect output.
0
PLL1 is in lock.
1
PLL1 is out of lock.
TCK
CKOP, CKON
CHAP1
92
18, 19
84
LVTTL IN
CML OUT
ANL OUT
CHAP2
93
ANL OUT
VBB
VBBS
NLOCK1
23, 61
22
77
ANL IN
ANL OUT
PCMOS OUT
Data Sheet Rev.: 16
GD16523
Page 3 of 10
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