2.5 Gbit/s
16:1 Multiplexer
GD16523
Preliminary
General Information
The GD16523 multiplexes sixteen data
inputs into a single data output, the bit
rates of the inputs are selectable (see
table below).
The data inputs are forward clocked by
the differential input (DCLKP / DCLKN).
The GD16523 tolerates up to 1.7 UI
PP
(155 MHz) jitter on the input data and for-
ward clock.
A double PLL system combined with an
elastic buffer ensures low output jitter.
Each PLL has a separate PCMOS lock-
detect output.
VBB
VBBS
Features
The VCXO reference clock input is differ-
ential and the frequency is selectable
78 MHz or 155 MHz.
Data inputs are differential LVPECL in-
puts. 2.5 GHz clock and data outputs are
differential CML with internal 50
Ω
termi-
nations.
The GD16523 requires only one supply
voltage of +3.3 V and consumes less
than 1 W.
The GD16523 is available in a 100 pin
TQFP package (14 × 14 mm) with heat
slug on bottom surface.
LSEL
SLBOP
SLBON
l
l
l
l
l
l
l
l
2.5 Gbit/s 16:1 Multiplexer.
Forward clocked input data.
Differential reference clock input.
2.5 GHz clock output.
LVTTL lock detect outputs.
Single power supply: +3.3 V.
Power consumption: less than 1 W.
Available in a 100 pin TQFP package
(14 × 14 mm) with exposed heat slug
on bottom surface.
DIP0
DIN0
DIP15
DIN15
DCLKP
DCLKN
16
16
Elastic
Buffer
IBR
W
IBR/2
IBR/2
R
IBR
16:1
MUX
OBR
DOUTP
DOUTN
/2
Narrow
band
LPF
CHAP1
CKOP
CKON
PFD1
/2
Clock
Generator
BRS0
BRS1
NLOCK1
NLDC1
CSEL
NLOCK2
VCXIP
VCXIN
PFD2
VCO
2.5 GHz
CHAP2
XSEL
SLTCK TCK
VCTL
NLDC2
VEE
VEEA
VCC
VCCA
VCXO
72 - 81 MHz
143 - 163 MHz
IBR = Input Bit Rate
OBR = Output Bit Rate
Wideband
LPF
BRS1
0
0
1
1
Data Sheet Rev. 11
BRS0
0
1
0
1
Input Bit Rate (IBR)
9.0 - 10.1 Mbit/s
36 - 40 Mbit/s
72 - 81 Mbit/s
143 - 163 Mbit/s
Output Bit Rate (OBR)
143 - 163 Mbit/s
575 - 650 Mbit/s
1150 - 1300 Mbit/s
2300 - 2600 Mbit/s
Functional Details
The GD16523 multiplexes the sixteen
data inputs (DIP/N0-15) into a single
data output (DOUT) with DIP/N0 as the
first bit to be output and DIP/N15 as the
last. The data inputs are differential
LVPECL type and the output is differen-
tial CML, driving 10 mA in a 50
Ω
load
connected to VCC. Furthermore the input
data is forward clocked by the DCLK
input.
To reduce noise on the output to a mini-
mum a double PLL system has been im-
plemented. The first PLL in addition to a
passive loop filter requires an external
crystal VCO (VCXO). The centre fre-
quency of the VCXI input which is driven
by the external VCXO can be selected to
be in either range 143 - 163 MHz or 72 -
81 MHz by the XSEL pin. The second
PLL requires only a passive external loop
filter typically consisting of a resistor and
a capacitor.
The noise performance on the output of
the chip depends on three noise generat-
ing sources, the forward clock (DCLK),
the external VCO (VCXO) and the inter-
nal VCO, see
Figure 1.
The output noise
is a combination of theese three curves.
First the noise follows the DCLK curve
until the loop-bandwidth of LPF1 then the
noise follows the curve of VCXO until the
loop-bandwidth of LPF2, and finally it fol-
lows the noise of the internal VCO, see
Figure 2.
Above the PLL1 loop-filter frequency the
noise performance is determined by the
VCXO therefore the PLL1 loop-filter fre-
quency should be set as low as possible.
At the same time the the jitter on the for-
ward clock integrated at frequencies
above the PLL1 loop-filter frequency may
not exceed 1.7 UI
PP
(155 MHz). The opti-
mum PLL1 loop bandwidth is therefore
the frequency above which the integrated
noise is just below 1.7 UI
PP
(155 MHz).
The optimum loop bandwidth of PLL2 is
the frequency where the VCO curve
crosses the VCXO curve, see
Figure 1.
A PCMOS lock detect output pin is avail-
able for each PLL, indicating if the corre-
sponding PLL is in lock. To enable this
function a 5 - 10 nF capacitor should be
connected to each of the NLDC pins.
This capacitor filters the NLDET signal
generated internally by XORing the two
signals going to the PFD and putting this
through a charge pump to the NLDC pin.
This filtering enables the NLOCK pin to
go low when the corresponding PLL is in
lock and high when out of lock.
A high level on the CSEL input bypasses
the PLL1 so that the write signal to the
elastic buffer goes directly to the PFD2. It
also bypasses the divider between the
Clock Generator and the PFD2. Note that
changing the bit rate in this mode
changes the loop-bandwidth of the PPL2.
The auxillary output SLBOP/SLBON is a
second data output to accommodate
near-end loop back. To save power in
normal operation and reduce noise in the
receiver the output can be turned off by
setting LSEL low.
The two bit rate select signals BRS1 and
BRS0 select the bit rate of the chip.
BRS1
1
1
0
0
BRS0
1
0
1
0
DIP/N0..15
155 Mbit/s
77 Mbit/s
38 Mbit/s
9.7 Mbit/s
DOUTP/N
2.5 Gbit/s
1.25 Gbit/s
622 Mbit/s
155 Mbit/s
Application Details
PLL Loop Filters
The loop filters can be made as shown in
Figure 3.
The values in
Figure 3
are the
same as used in the production test sets.
For optimal jitter performance the values
of LPF1 should be adjusted according to
the jitter on the input data and the values
for LPF2 should be adjusted according to
the jitter on the VCXO.
CHAP1
R1
C1
VCC
PFD1
VCXIP
VCXIN
PFD2
VCO
VCXO
CHAP2
R2
C2
VCCA
VCTL
Figure 3.
Loop Filters
For noise and jitter reasons it is important
that the capacitor (C2) is connected to
VCCA close to the VCTL pin.
Signal Power
From
DCLK
From
VCXO
From
VCO
Frequency
Biasing the Data Inputs
All the data inputs are biased internally
on the chip with the resistive network as
shown in
Figure 4 .
The data inputs can be used both differ-
ential and single-ended without any ex-
ternal pull-ups/downs and can also be
AC-coupled.
The VBB input may be shorted to the
VBBS output and de-copled with at least
one external capacitor on either pin 23 or
61.
Figure 1.
Noise sources contributing to
the output noise. Normalized
to same signal power and
carrier frequency.
Signal Power
LBW1
LBW2
Frequency
DIP0
DIN0
5kΩ
VBB
5kΩ
DIP15
DIN15
5kΩ
5kΩ
Figure 2.
Spectrum of output clock, with
optimized LBW2.
Figure 4.
Data Inputs
Data Sheet Rev. 11
GD16523
Page 2 of 10
Pin List
Mnemonic:
DIP0
DIP1
DIP2
DIP3
DIP4
DIP5
DIP6
DIP7
DIP8
DIP9
DIP10
DIP11
DIP12
DIP13
DIP14
DIP15
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
Pin numbers:
26, 27
28, 29
30, 31
32, 33
34, 35
36, 37
39, 40
41, 42
43, 44
45, 46
47, 48
49, 50
53, 54
55, 56
57, 58
59, 60
63, 64
88, 89
96
71
72
Pin Type:
LVPECL IN
Description:
Differential data inputs multiplexed to the serial output starting
with DIP0, followed by DIP1, DIP2....DIP15. Pre-biased to VBB.
DCLKP, DCLKN
VCXIP, VCXIN
VCTL
CSEL
LSEL
LVPECL IN
LVPECL IN
ANL IN
LVTTL IN
LVTTL IN
Differential clock input. These pins are used to forward clock the
data inputs.
Differential VCXO clock input for PLL1.
Internal VCO frequency control input.
PLL1 bypass select signal. Low PLL1 is active. High PLL1 is by-
passed. Unconnected is same as Low.
Loop select. When LSEL is low SLBOP/N output buffer is
powered down, when LSEL is high it is powered up. Unconnected
is same as Low.
Select input for reference clock frequency. Low selects 77 MHz;
high selects 155 MHz. Unconnected is same as High.
Bit rate select. Unconnected selects 1,1.
BRS1
1
1
0
0
BRS0
1
0
1
0
DIP0..DIP15 DOUTP/N
155.52 Mbit/s 2.488 Gbit/s
77.76 Mbit/s 1.244 Gbit/s
38.88 Mbit/s
622 Mbit/s
9.72 Mbit/s
155 Mbit/s
XSEL
BRS0, BRS1
73
68, 69
LVTTL IN
LVTTL IN
DOUTP, DOUTN
SLBOP, SLBON
SLTCK
TCK
CKOP, CKON
CHAP1
9, 10
3, 4
91
92
18, 19
84
CML OUT
CML OUT
LVTTL IN
LVTTL IN
CML OUT
ANL OUT
Multiplexed data output. On-chip terminated, refer to
Figure 6.
Near-end loop back output. On-chip terminated, refer to
Figure 6.
Clock source select input. Low selects internal VCO; high selects
TCK input as clock source. Unconnected is same as Low.
Test clock input. This pin is used as clock source instead of the
internal VCO when the SLTCK input pin is high.
Clock output in phase with the multiplexed data output. On-chip
terminated, refer to
Figure 6.
Charge-pump 1 output. Sinks current when VCXO is leading.
Sources current when VCXO is lagging, use positive transfer
VCXO.
Charge-pump 2 output. Sources current when internal VCO is
leading. Sinks current when internal VCO is lagging. Internal VCO
is negative transfer.
Reference voltage input for differential data inputs.
Reference voltage output for differential data inputs.
PLL1 lock detect output.
High when PLL1 is out of lock. Low when PLL1 is in lock.
PLL2 lock detect output.
High when PLL2 is out of lock. Low when PLL2 is in lock.
A capacitor should be connected to this pin to set the time con-
stant for the NLOCK1 output.
CHAP2
93
ANL OUT
VBB
VBBS
NLOCK1
NLOCK2
NLDC1
23, 61
22
77
78
80
ANL IN
ANL OUT
PCMOS OUT
PCMOS OUT
ANL IN/OUT
Data Sheet Rev. 11
GD16523
Page 3 of 10
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
