HD-LINX
™
GS1510
HDTV Serial Digital Deformatter
DATA SHEET
KEY FEATURES
• SMPTE 292M compliant
• standards detection/indication for SMPTE 292M levels
A/B,C,D/E,F,G/H,I,J/K,L/M
• NRZI decoding and SMPTE descrambling with
BYPASS option
• line CRC calculation, comparison
• selectable line based CRC re-Insertion
• H, V, F timing reference signal (TRS) extraction
• selectable flywheel for noise immune H, V, F extraction
• selectable automatic switch line handling
• selectable TRS and line number re-insertion
• selectable active picture illegal code re-mapping
• configurable FIFO LOAD pulse
• Pb-free and Green
• 20 bit 3.3V CMOS input data bus
• optimized input interface to GS1545 or GS1540
• single +3.3V power supply
• 5V tolerant I/O
APPLICATIONS
•
SMPTE 292M Serial Digital Interfaces
DESCRIPTION
When interfaced to the Gennum GS1545 HDTV Equalizing
Receiver or GS1540 Non-Equalizing Receiver, the GS1510
performs the final conversion to word aligned data. The
device performs NRZI decoding and de-scrambling as per
SMPTE 292M and word-aligns to the incoming data stream.
Line based CRCs are calculated on the incoming data
stream and are compared against the CRCs embedded
within the data stream.
HVF timing information is extracted from the data stream. A
selectable internal HVF flywheel provides superior noise
immunity against TRS signal errors. The device also detects
and indicates the input video signal standard.
The GS1510 can detect and re-map illegal code words
contained within the active portion of the video signal. Prior
to exiting the device, TRS, Line Numbers and CRCs based
on internal calculations may be re-inserted into the data
stream.
GS1510
WB_NI
BP_DSC
BP_FR
3
FW_EN/DIS
FAST_LOCK
2
RESET
TRS_Y/C
F_E/S
2
MUTE
CODE
PROTECT
TRS_INS
LN_INS
CRC_INS
3
DATA_IN
[19:0]
INPUT
BUFFER
DESCRAMBLE
FRAME
TRS DETECTION
CRC CALCULATION
FLYWHEEL
CRC COMPARISON
STANDARD DETECTION
ILLEGAL CODE REMAPPING
TRS EXTRACTION
TRS,
LNUM,
AND CRC
INSERTION
DATA_OUT
[19:10]
(LUMA)
DATA_OUT
[9:0]
(CHROMA)
PCLK_IN
3
[H:V:F]
3
FIFO_L
4
2
LINE_CRC_ERR [Y:C]
OEN
LN_ERR
SAV_ERR
EAV_ERR
VD_STD [3:0]
GS1510 FUNCTIONAL BLOCK DIAGRAM
Revision Date: June 2004
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No.
52247 - 4
TABLE OF CONTENTS
1. PIN OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PIN ASSIGNMENT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
2. ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 ABSOLUTE MAXIMUM RATINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GS1510
3. DETAILED DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
4. REFERENCES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. PACKAGE & ORDERING INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 PACKAGE DIMENSIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 ORDERING INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 of 12
GENNUM CORPORATION
52247 - 4
1. PIN OUT
EAV_ERR
LN_ERR
SAV_ERR
V
DD
TEST
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
V
DD
V
DD
V
DD
V
DD
1.1 PIN ASSIGNMENT
GND
GND
GND
GND
GND
GND
GND
GS1510
GENNUM CORPORATION
99
65
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
102
101
100
DATA_IN[19]
DATA_IN[18]
DATA_IN[17]
DATA_IN[16]
DATA_IN[15]
DATA_IN[14]
DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
V
DD
GND
DATA_OUT[14]
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
DATA_OUT[9]
V
DD
GND
DATA_OUT[8]
DATA_OUT[7]
V
DD
GND
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
V
DD
GND
DATA_IN[13]
DATA_IN[12]
DATA_IN[11]
DATA_IN[10]
GS1510
TOP
VIEW
3 of 12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
F
V
H
NC
NC
V
DD
V
DD
V
DD
GND
GND
GND
GND
GND
F_E/S
MUTE
BP_FR
RESET
WB_NI
LN_INS
BP_DSC
TRS_Y/C
TRS_INS
PCLK_IN
CRC_INS
VD_STD[3]
FW_EN/DIS
FAST_LOCK
CODE_PROTECT
V
DD
GND
DATA_IN[9]
DATA_IN[8]
DATA_IN[7]
DATA_IN[6]
DATA_IN[5]
DATA_IN[4]
DATA_IN[3]
DATA_IN[2]
DATA_IN[1]
DATA_IN[0]
V
DD
GND
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
29
VD_STD[2]
30
VD_STD[1]
31
VD_STD[0]
32
LINE_CRC_ERR_C
33
LINE_CRC_ERR_Y
34
FIFO_L
35
TN
36
OEN
37
GND
38
V
DD
52247 - 4
1.2 PIN DESCRIPTIONS
PIN
NUMBER
1
NAME
PCLK_IN
TIMING
Synchronous
wrt PCLK_IN
TYPE
Input
DESCRIPTION
Input Clock.
The device uses PCLK_IN for clocking the input data
stream into DATA_IN[19:0]. This clock is generated by the GS1545
or GS1540
Ground power supply connections.
2, 4, 14, 19,
24, 37, 46,
50, 58, 69,
79, 82, 91,
94, 110,
116, 128
3, 20, 25,
38, 47, 51,
59, 68, 78,
81, 90, 93,
109, 115,
127
5
GND
Gnd
GS1510
V
DD
Power
Positive power supply connections.
F_E/S
Non-
synchronous
Input
Control Signal Input.
Used to control where the FIFO_L signal is
generated. When F_E/S is high, the GS1510 generates FIFO_L
signal at EAV. When F_E/S is low, the GS1510 generates FIFO_L
signal at SAV. See Fig. 4 for timing information.
Control Signal Input.
Used to enable or disable blanking of the
LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). When
MUTE is low, the device sets the accompanying LUMA and
CHROMA data to their appropriate blanking levels. When MUTE is
high, the LUMA and CHROMA data streams pass through this stage
of the device unaltered.
Control Signal Input.
Used to enable or disable the internal
flywheel. When FW_EN/DIS is high, the internal flywheel is enabled.
When FW_EN/DIS is low, the internal fly-wheel is disabled.
Control Signal Input.
Used to enable or disable re-mapping of out-
of-range words contained in the active portion of the video signal.
When this signal is high, the device re-maps out-of-range words
contained within the active portion of the video signal into CCIR-601
compliant words. Values between
000-003 are re-mapped to
004. Values between 3FC and 3FF are re-mapped to 3FB. When this
signal is low, out-of-range words in the active video region pass
through the device unaltered.
Control Signal Input.
Used to enable or disable word boundary
framing. When BP_FR is low internal framing is enabled. When
BP_FR is high internal framing is bypassed.
Control Signal Input.
Used to enable or disable the SMPTE 292M
descrambler. When BP_DSC is low, the internal SMPTE 292M
descrambler is enabled. When BP_DSC is high, the internal SMPTE
292M de-scrambler is bypassed.
Control Signal Input.
Used to enable or disable noise immune
operation of the word boundary framer. When WB_NI is high, noise-
immune word boundary alignment is enabled. The device switches
to a new word boundary only when it has detected two consecutive
identical new TRS positions. When WB_NI is low, the device re-
aligns the word boundary position at every instance of a TRS.
Control Signal Input.
Used to control whether LUMA or CHROMA
TRS IDs are detected and used. When TRS_Y/C is high, the device
detects and uses TRS signals embedded in the LUMA channel.
When TRS_Y/C is low, the device detects and uses TRS signals
embedded in the CHROMA channel.
6
MUTE
Synchronous
wrt PCLK_IN
Input
7
FW_EN/DIS
Non-
synchronous
Input
8
CODE_PROTECT
Non-
synchronous
Input
9
BP_FR
Non-
synchronous
Input
10
BP_DSC
Non-
synchronous
Input
11
WB_NI
Non-
synchronous
Input
12
TRS_Y/C
Non-
synchronous
Input
4 of 12
GENNUM CORPORATION
52247 - 4
1.2 PIN DESCRIPTIONS
(Continued)
PIN
NUMBER
13
NAME
TRS_INS
TIMING
Non-
synchronous
TYPE
Input
DESCRIPTION
Control Signal Input.
Used to enable or disable re-insertion of the
TRS into the data stream. When TRS_INS is high, the device re-
inserts TRS into the incoming data stream based on the internal
calculation. The original TRS packets are set to the blanking levels.
If the flywheel is enabled, TRS calculated by the flywheel is used for
insertion. When TRS_INS is low, the device will not re-insert TRS
even if errors in TRS signals are detected.
Control Signal Input.
Used to enable or disable re-insertion of the
line number into the data stream. When LN_INS is high, the device
re-inserts the line number into the incoming data stream based on
the internal calculation. The original line number packets are set to
the blanking levels. If the flywheel is enabled, the line number
calculated by the flywheel is used for insertion. When LN_INS is low,
the device will not re-insert the line number.
Control Signal Input.
Used to enable or disable re-insertion of the
CRC into the data stream. When CRC_INS is high, the device is
enabled to re-insert line CRCs based on the internal calculation.
When CRC_INS is low, the device will not re-insert the CRCs.
Control Signal Input.
Used to control the flywheel synchronization
when a switch line occurs. When a low to high transition occurs on
the FAST_LOCK signal, the internal flywheel will immediately re-
synchronize to the next valid EAV or SAV TRS in the incoming data
stream. See Fig. 5 for timing information.
Control Signal Input.
Used to reset the system state registers to their
default 720p parameters. When RESET is high, the fly wheel, TRS
Detection, and ANC Detection operate normally. When RESET is low,
the flywheel, TRS Detection, and ANC Detection are reset to the
720p parameters after a rising edge on PCLK_IN. The read and
write counters are not affected.
Control Signal Output.
This signal indicates the Horizontal blanking
period of the video signal. Refer to Fig. 2 for timing information of H
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.
Control Signal Output.
This signal indicates the Vertical blanking
period of the video signal. Refer to Fig. 2 for timing information of V
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.
Control Signal Output.
This signal indicates the ODD/EVEN field of
the video signal. Refer to Fig. 2 for timing information of F relative to
DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA
respectively. When locked and the input signal is of a progressive
scan nature, F stays low at all times.
No Connect.
Do not connect these pins.
GS1510
15
LN_INS
Non-
synchronous
Input
16
CRC_INS
Non-
synchronous
Input
17
FAST_LOCK
Synchronous
wrt PCLK_IN
Input
18
RESET
Non-
synchronous
Input
21
H
Synchronous
wrt PCLK_IN
Output
22
V
Synchronous
wrt PCLK_IN
Output
23
F
Synchronous
wrt PCLK_IN
Output
26,27,71-
77,80,
83-89
28, 29, 30,
31
NC
N/A
N/A
VD_STD[3:0]
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
VD_STD[3:0] indicates which input video
standard the device has detected. The GS1510 will indicate all of
the formats in SMPTE292M (see Table 1) plus it will indicate an
unknown interlace or progressive scan format.
5 of 12
GENNUM CORPORATION
52247 - 4
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