Latch Up Current ..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V
CC
Relative to GND
[2]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[2]
................................... –0.5V to V
CC
+ 0.5V
Operating Range
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL[2]
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, output disabled
V
CC
= Max, f = f
MAX
= 1/t
RC
I
OUT
= 0 mA CMOS levels
Test Conditions
[3]
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
2.0
–0.3
–1
–1
–10
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
175
30
25
Max
Unit
V
V
V
V
μA
μA
mA
mA
mA
Automatic CE Power Down Max V
CC
, CE > V
IH
Current —TTL Inputs
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Automatic CE Power Down Max V
CC
, CE > V
CC
– 0.3V,
Current — CMOS Inputs
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V, f = 0
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max
8
10
Unit
pF
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
119-Ball
PBGA
20.31
8.35
Unit
°C/W
°C/W
Notes
2. V
IL
(min) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. CE refers to a combination of CE
1
, CE
2
, and CE
3
. CE is LOW when CE
1
, CE
3
are LOW and CE
2
is HIGH. CE is HIGH when CE
1
is HIGH, or CE
2
is LOW, or CE
3
is HIGH.
Document Number: 001-08353 Rev. *C
Page 3 of 9
[+] Feedback
CY7C1024DV33
Figure 2. AC Test Loads and Waveform
[4]
50Ω
OUTPUT
Z0 = 50Ω
30 pF*
V
TH
= 1.5V
3.3V
OUTPUT
5 pF*
R1 317
Ω
R2
351Ω
(a)
*Capacitive Load consists of all
components of the test environment
*
Including jig
and scope
(b)
All input pulses
3.0V
GND
90%
10%
(c)
90%
10%
Fall Time:> 1V/ns
Rise Time > 1V/ns
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
V
CC
(Typical) to the First Access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE Active LOW to Data Valid
[3]
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[7]
CE Active LOW to Low Z
[3, 7]
CE Deselect HIGH to High Z
[3, 7]
CE Active LOW to Power Up
[3, 8]
CE Deselect HIGH to Power Down
[3, 8]
0
10
3
5
1
5
3
10
5
100
10
10
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
–10
Min
Max
Unit
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). 100
μs
(t
power
) after reaching the minimum operating
V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of
Figure 2,
unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
7. t
HZOE
, t
HZCE
, t
HZWE
, t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in part (b) of
Figure 2.
Transition is measured
±200
mV from steady state
voltage.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-08353 Rev. *C
Page 4 of 9
[+] Feedback
CY7C1024DV33
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Write Cycle
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
(continued)
Description
–10
Min
10
7
7
0
0
7
5.5
0
3
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE active LOW to Write End
[3]
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[7]
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR [11]
t
R [12]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 2V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
0
t
RC
Conditions
[3]
Min
2
25
Typ
Max
Unit
V
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0V
t
CDR
V
DR
>
2V
3.0V
t
R
Notes
9. The internal write time of the memory is defined by the overlap of CE
1
and CE
2
and CE
3
LOW and WE LOW. Chip enables must be active and WE must be LOW to
initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that
terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
11. Tested initially and after any design or process changes that may affect these parameters.
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