Preliminary
GS88418/36B-200/180/166/150/133
119-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipelined
operation
• Single/Dual Cycle Deselect Selectable
• ZQ mode pin for user-selectable high/low output drive strength
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 119-bump BGA package
512K x 18, 256K x 36
8Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
200 MHz–133 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
(LBO) input. The Burst function need not be used. New
addresses can be loaded on every cycle with no degradation of
chip performance.
The function of the Data Output register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS88436B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
-200
5.0
3.0
450
7.5
10
270
-180
5. 5
3.2
410
8
10
270
-166
6.0
3.5
380
8.5
10
250
-150
6.7
3.8
350
9.0
10
240
-133
7.5
4.0
340
9.5
10
220
Unit
ns
ns
mA
ns
ns
mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
The GS88418/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Controls
Addresses, data I/Os, chip enables (E1, in x18 version, E1 and
E2 in x36 version), address burst control inputs (ADSP,
ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered
clock input (CK). Output enable (G) and power-down control
(ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order
Rev: 1.05 10/2001
1/25
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS884B operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuit.
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88436 Pad Out
119-Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C4
DQ
C3
V
DDQ
DQ
C2
DQ
C1
V
DDQ
DQ
D1
DQ
D2
V
DDQ
DQ
D3
DQ
D4
NC
NC
V
DDQ
2
A
6
E
2
A
5
DQ
PC9
DQ
C8
DQ
C7
DQ
C6
DQ
C5
V
DD
DQ
D5
DQ
D6
DQ
D7
DQ
D8
DQ
PD9
A
2
NC
NC
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
C
V
SS
NC
V
SS
B
D
V
SS
V
SS
V
SS
LBO
A
10
NC
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
A
11
NC
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
NC
6
A
9
A
17
A
16
DQ
PB9
DQ
B8
DQ
B7
DQ
B6
DQ
B5
V
DD
DQ
A5
DQ
A6
DQ
A7
DQ
A8
DQ
PA9
A
13
NC
NC
7
V
DDQ
NC
NC
DQ
B4
DQ
B3
V
DDQ
DQ
B2
DQ
B1
V
DDQ
DQ
A1
DQ
A2
V
DDQ
DQ
A3
DQ
A4
NC
ZZ
V
DDQ
Rev: 1.05 10/2001
2/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418 Pad Out
119-Bump BGA—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B1
NC
V
DDQ
NC
DQ
B4
V
DDQ
NC
DQ
B6
V
DDQ
DQ
B8
NC
NC
NC
V
DDQ
2
A
6
NC
A
5
NC
DQ
B2
NC
DQ
B3
NC
V
DD
DQ
B5
NC
DQ
B7
NC
DQ
B9
A
2
A
10
NC
3
A
7
A
4
A
3
V
SS
V
SS
V
SS
B
B
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
LBO
A
11
NC
4
ADSP
ADSC
V
DD
ZQ
E
1
G
ADV
GW
V
DD
CK
SCD
BW
A
1
A
0
V
DD
NC
NC
5
A
8
A
15
A
14
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
B
A
V
SS
V
SS
V
SS
FT
A
12
NC
6
A
9
A
17
A
16
DQ
A9
NC
DQ
A7
NC
DQ
A5
V
DD
NC
DQ
A3
NC
DQ
A2
NC
A
13
A
18
NC
7
V
DDQ
NC
NC
NC
DQ
A8
V
DDQ
DQ
A6
NC
V
DDQ
DQ
A4
NC
V
DDQ
NC
DQ
A1
NC
ZZ
V
DDQ
Rev: 1.05 10/2001
3/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418/36 BGA Pin Description
Pin Location
P4, N4
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, G4, R2, R6, T3, T5
T4
T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
L5, G5, G3, L3
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
L5, G3
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4
K4
E4
B2
F4
T7
R5
R3
L4
D4
B1, C1, R1, T1, L4, B7, C7, U6, R7,
J3,J5, U2, U3, U4, U5
J2, C4, J4, R4, J6
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
A1, F1, J1, M1, U1, A7, F7, J7, M7,
U7
Symbol
A
0
, A
1
An
An
NC
An
DQ
A1
–DQ
PA9
DQ
B1
–DQ
PB9
DQ
C1
–DQ
PC9
DQ
D1
–DQ
PD9
B
A
, B
B
, B
C
, B
D
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
B
A
, B
B
NC
CK
E
1
E
2
G
ZZ
FT
LBO
SCD
ZQ
NC
V
DD
V
SS
V
DDQ
Type
I
I
I
—
I
I/O
I
I/O
I
—
I
I
I
I
I
I
I
I
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
Data Input and Output pins (x36 Version)
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low ( x36 Version)
Data Input and Output pins (x18 Version)
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low ( x18 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
No Connect
Core power supply
I/O and Core Ground
Output driver power supply
BPR2000.002.14
Rev: 1.05 10/2001
4/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88418/36B-200/180/166/150/133
GS88418/36 Block Diagram
Register
A0–An
D
Q
A0
D0
A1
D1
Q1
Counter
Load
A
Q0
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
D
Register
D
B
B
Q
18
4
18
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
Register
E
1
D
Q
Register
D
FT
G
Power Down
Control
Q
ZZ
DCD=0
SCD=1
DQx0–DQx9
Note: Only x18 version shown for simplicity.
Rev: 1.05 10/2001
5/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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