IS61VPS25672A IS61LPS25672A
IS61VPS51236A IS61LPS51236A
IS61VPS102418A IS61LPS102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPS: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VPS: V
DD
2.5V + 5%, V
DDQ
2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
PBGA, and 209-ball (x72) packages
• Lead-free available
JANUARY 2010
DESCRIPTION
The
ISSI
IS61LPS/VPS51236A, IS61LPS/VPS102418A,
and IS61LPS/VPS25672A are high-speed, low-power syn-
chronous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LPS/VPS51236A is organized as
524,288 words by 36 bits, the IS61LPS/VPS102418A is
organized as 1,048,576 words by 18 bits, and the IS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with
ISSI
's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. M
01/10/2010
1
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
A
BWc
BWh
VSS
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
CLK
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
VSS
NC
A
TMS
CE2
BWg
BWd
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
A
A
TDI
ADSP
NC
NC
NC
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
NC
A
A
A
ADSC
BWE
CE
OE
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
ZZ
V
DD
MODE
A
A1
A0
ADV
A
NC
GW
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
VSS
V
DD
NC
A
A
A
CE2
BWb
BWe
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
A
A
TDO
9
A
BWf
BWa
VSS
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
NC
V
DDQ
VSS
V
DDQ
VSS
V
DDQ
VSS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2,
CE2
BWx
(x=a,b,c,d
e,f,g,h)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
V
DD
V
DDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V
/2.5V
Ground
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. M
01/20/2010
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