Preliminary
GS8672Q18/36AE-333/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and
144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaQuad-II™
Burst of 2 ECCRAM™
Clocking and Addressing Schemes
333 MHz–200 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
The GS8672Q18/36AE SigmaQuad-II ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
High, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B2
ΕCCRAMs
always
transfer data in two packets, A0 is internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfer. Because the LSB is tied off internally, the
address field of a SigmaQuad-II B2 ECCRAM is always one
address pin less than the advertised index depth (e.g., the 4M x
18 has a 2048K addressable index).
SigmaQuad™ ECCRAM Overview
The GS8672Q18/36AE SigmaQuad-II ECCRAMs are built in
compliance with the SigmaQuad-II SRAM pinout standard for
Separate I/O synchronous SRAMs. They are 75,497,472-bit
(72Mb) ECCRAMs. The GS8672Q18/36AE SigmaQuad-II
ECCRAMs are just one element in a family of Low power,
Low voltage HSTL I/O ECCRAMs designed to operate at the
speeds needed to implement economical High performance
networking systems.
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the
Byte
Write Contol
section for further information.
Parameter Synopsis
-333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.02 5/2010
1/27
© 2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8672Q18/36AE-333/300/250/200
Pin Description Table
Symbol
SA
R
W
BW0–BW3
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
Qn
Dn
Description
Synchronous Address Inputs
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Input Clock
Input Clock
Output Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when Low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
No Connect
No Function
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Supply
Supply
Supply
—
—
Comments
—
Active Low
Active Low
Active Low
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
—
Active Low
—
—
1.8 V Nominal
1.5 or 1.8 V Nominal
—
—
—
Doff
CQ
CQ
V
DD
V
DDQ
V
SS
NC
NF
Notes:
1. NC = Not Connected to die or any other pin.
2. NF= No Function. There is an electrical connection to this input pin, but the signal has no function in the device. It can be left unconnected,
or tied to V
SS
or V
DDQ.
3. C, C, K, or K cannot be set to V
REF
voltage.
Rev: 1.02 5/2010
4/27
© 2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8672Q18/36AE-333/300/250/200
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II ECCRAM interface and truth table are optimized for alternating reads and writes. Separate
I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers
from Separate I/O ECCRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II ECCRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted.
- R and W High always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the
Truth Table
for
details.
SigmaQuad-II B2 ECCRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A Low on the Read Enable pin, R, begins
a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied High), and
after the following rising edge of K with a rising edge of C (or by K if C and C are tied High). Clocking in a High on the Read
Enable pin, R, begins a read port deselect cycle.
SigmaQuad-II B2 ECCRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A Low on the Write Enable pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a High on W causes a write port deselect cycle.
Rev: 1.02 5/2010
5/27
© 2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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