NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
NM27C040
March 1997
NM27C040
4,194,304-Bit (512K x 8) High Performance CMOS
EPROM
General Description
The NM27C040 is a high performance, 4,194,304-bit Electri-
cally Programmable UV Erasable Read Only Memory. It is
organized as 512K words of 8 bits each. Its pin-compatibility
with byte-wide JEDEC EPROMs enables upgrades through
8 Mbit EPROMs. The “Don’t Care” feature on V
PP
during
read operations allows memory expansions from 1M to
8 Mbits with no printed circuit board changes.
The NM27C040 provides microprocessor-based systems
extensive storage capacity for large portions of operating
system and application software. Its 120 ns access time pro-
vides high speed operation with high-performance CPUs.
The NM27C040 offers a single chip solution for the code
storage requirements of 100% firmware-based equipment.
Frequently used software routines are quickly executed from
EPROM storage, greatly enhancing system utility.
The NM27C040 is manufactured using Fairchild’s advanced
CMOS AMG
™
EPROM technology.
Features
n
High performance CMOS
— 120 ns access time
n
Simplified upgrade path
— V
PP
is a “Don’t Care” during normal read operation
n
Manufacturer’s identification code
n
JEDEC standard pin configuration
— 32-pin DIP
— 32-pin PLCC
— 32-pin TSOP
Block Diagram
DS010836-1
AMG
™
is a trademark of WSI, Inc.
© 1997 Fairchild Semiconductor Corporation
DS010836
www.fairchildsemi.com
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PrintDate=1997/08/11 PrintTime=19:20:20 6769 ds010836 Rev. No. 3
cmserv
Proof
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Connection Diagrams
DS010836-2
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.
Commercial Temperature Range
(0˚C to +70˚C)
V
CC
= 5V
±
10%
Parameter/Order Number
NM27C040 Q, V, T 120
NM27C040 Q, V, T 150
NM27C040 Q, V, T 170
NM27C040 Q, V, T 200
Access Time (ns)
120
150
170
200
Extended Temperature Range
(−40˚C to +85˚C)
V
CC
= 5V
±
10%
Parameter/Order Number
NM27C040 QE, VE, TE 150
NM27C040 QE, VE, TE 170
NM27C040 QE, VE, TE 200
Package Types: NM27C040 Q, V, T XXX
Q = Quartz-Windowed Ceramic DIP
V = PLCC
T = TSOP
Access Time (ns)
150
170
200
Military Temperature Range (−55˚C
to +125˚C)
V
CC
= 5V
±
10%
Parameter/Order Number
NM27C040 QM 150
NM27C040 QM 200
Access Time (ns)
150
200
•
•
All packages conform to the JEDEC standard.
All versions are guaranteed to function for slower speeds.
Pin Names
A0–A18
CE /PGM
OE
O0–O7
XX
Addresses
Chip Enable/Program
Output Enable
Outputs
Don’t Care (During Read)
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PrintDate=1997/08/11 PrintTime=19:20:21 6769 ds010836 Rev. No. 3 cmserv
Proof
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Absolute Maximum Ratings
Storage Temperature
All Input Voltages except A9 with
Respect to Ground
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
All Output Voltages with
(Note 1)
Respect to Ground
V
CC
+10V to GND −0.6V
−65˚C to +150˚C
Operating Range
−0.6V to +7V
−0.6V to +14V
−0.6V to +7V
>
2000V
Range
Commercial
Industrial
Temperature
0˚C to +70˚C
−40˚C to +85˚C
V
CC
+5V
+5V
Tolerance
±
10%
±
10%
Read Operation
DC Electrical Characteristics
Over operating range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current (CMOS)
V
CC
Standby Current
V
CC
Active Current
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
I
OL
= 2.1 mA
I
OH
= −2.5 mA
CE = V
CC
±
0.3V
CE = V
IH
CE = OE = V
IL
, I/O = 0 mA
V
PP
= V
CC
Test Conditions
Min
−0.5
2.0
3.5
100
1
f = 5 MHz
V
CC
− 0.4
−1
−10
30
10
V
CC
1
10
Max
0.8
V
CC
+ 1
0.4
Units
V
V
V
V
µA
mA
mA
µA
V
µA
µA
AC Electrical Characteristics
Over operating range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to
Output Float
Output Hold from Addresses
CE or OE , Whichever
Occurred First
0
0
0
0
120
Max
120
120
50
35
Min
150
Max
150
150
50
35
Min
170
Max
170
170
50
45
Min
200
Max
200
200
50
55
ns
Units
Capacitance
T
A
= +25˚C, f = 1 MHz (Note 2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
9
12
Max
15
15
Units
pF
pF
AC Test Conditions
Output Load
Input Rise and Fall Times
1 TTL Gate and
C
L
= 100 pF (Note 8)
≤5
ns
Input Pulse Levels
Inputs
Outputs
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Timing Measurement Reference Level (Note 10)
3
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PrintDate=1997/08/11 PrintTime=19:20:24 6769 ds010836 Rev. No. 3 cmserv
Proof
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AC Waveforms
(Notes 6, 7, 9)
DS010836-4
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
− t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) − 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on
every device between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= −400 µA.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to −2.0V for 20 ns Max.
Programming Waveform
(Note 13)
DS010836-5
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PrintDate=1997/08/11 PrintTime=19:20:26 6769 ds010836 Rev. No. 3 cmserv
Proof
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Programming Characteristics
Symbol
t
AS
t
OES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
OE Setup Time
Data Setup Time
V
PP
Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
V
PP
Supply Current during
Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Parameter
Address Setup Time
(Notes 11, 12, 13, 14)
Conditions
Min
1
1
1
1
1
0
1
CE /PGM = X
CE /PGM = X
CE /PGM = V
IL
0
45
50
60
105
100
30
30
20
6.25
12.5
5
−0.1
2.4
0.8
0.8
0.0
4.0
2.0
2.0
0.45
25
6.5
12.75
30
6.75
13.0
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
mA
mA
˚C
V
V
ns
V
V
V
V
Note 11:
Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a
board with voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across V
PP
, V
CC
to GND to suppress spurious
voltage transients which may damage the device.
Note 14:
During power up the CE /PGM pin must be brought high (≥V
IH
) either coincident with or before power is applied to V
PP
.
5
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PrintDate=1997/08/11 PrintTime=19:20:27 6769 ds010836 Rev. No. 3 cmserv
Proof
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