CALIFORNIA MICRO DEVICES
CALIFORNIA MICRO DEVICES
PAC DN006
Applications
I/O port protection for cellular
phones, notebook computers, PDAs, etc.
ESD protection for VGA (Video) port in
PCs or Notebook computers
ESD protection for sensitive
electronic equipment.
6 CHANNEL ESD PROTECTION ARRAY
Features
Six channels of ESD protection
15KV ESD protection (HBM)
8KV contact, 15KV air ESD protection
per IEC 1000-4-2
Low loading capacitance, 3 pF typ.
Miniature 8-pin MSOP or SOIC package
Product Description
The PAC DN006 is a diode array designed to provide 6 channels of ESD protection for electronic components or sub-
systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V
P
) or
negative (V
N
) supply. The PAC DN006 will protect against ESD pulses up to 15 KV Human Body Model (100 pF
capacitor discharging through a 1.5K
Ω
resistor) and 8KV contact discharge per International Standard IEC1000-4-2.
This device is particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because
of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting
video output lines and I/O ports in computers and peripheral equipment.
ABSOLUTE MAXIMUM RATINGS
SCHEMATIC CONFIGURATION
Diode Forward DC Current
(Note 1)
20mA
°
Storage Temperature
-65 C to 150
°
C
Operating Temperature Range
0°C to 70°C
DC Voltage at any Channel Input V
N
-0.5V to V
P
+0.5V
Note 1: Only one diode conducting at a time.
Param e te r
Operating Supply Voltage ( V
P
-V
N
)
Diode Forward Voltage, I
F
= 20mA, T = 25°C
Diode reverse breakdown voltage, T = 25°C
ESD Protection
Peak Discharge Voltage at any Channel Input, in-system
(Note 2)
000
Human Body Model, Method 3015
(Note 3, 4)
000
Contact Discharge per IEC 1000-4-2
(Note 5)
000
Air Discharge per IEC 1000-4-2
(Note 5)
Channel Clamp Voltage @ 15KV ESD HBM, T = 25°C
000
Positive transients
000
Negative transients
Channel Leakage Current, T = 25°C
Channel Input Capacitance (Measured @ 1 MHz)
V
P
= 5V, V
N
= 0V, V
I N P U T
= 2 .5 V
Package Power Rating
000
SOIC Package
000
MSOP Package
Note
Note
Note
Note
2:
3:
4:
5:
STANDARD SPECIFICATIONS
Min.
0.65 V
17.0 V
±
15 KV
±
8KV
±
15KV
Typ.
M a x.
5.5 V
0.95 V
(Notes 3, 4)
0.1 µA
3pF
V
P
+13.0 V
V
N
-13.0 V
1.0 µA
6pF
350mW
200mW
From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with 0.2
µ
F ceramic capacitor.
Human Body Model per MIL-STD-883, Method 3015, C
Discharge
=100pF, R
Discharge
=1.5K
Ω
, V
P
=5.0V, V
N
=GND.
This parameter is guaranteed by design and characterization.
Standard IEC1000-4-2 with C
Discharge
=150pF, and R
Discharge
=330
Ω
, V
P
=5V, V
N
=GND.
©
Micro
California Micro Devices Corp.
© 1999 Calirornia
1999
Devices Corp. All rights reserved.
All rights reserved.
3/99 Rev 1
3/99 Rev. 1
PAC DN006 is a trademark of California Micro Devices Corp.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
Input Capacitance vs. Input Voltage
5
PAC DN006
Input Capacitance (pF)
4
3
2
1
0
0
1
2
3
4
5
Input Voltage
Typical variation of C
IN
with V
IN
. (V
P
=5V, V
N
=0V)
STANDARD PART ORDERING INFORMATION
Pa c k a g e
Orde ring Part N um be r
Pins
Style
Tube s
Tape & R e e l
8
8
SOIC
MSOP
PACDN006S/T
PACDN006M/T
PACDN006S/R
PACDN006M/R
Part Mark ing
PDN006S
D006
Application Information
See also California Micro Devices Application Note AP 209, Design Considerations for ESD Protection.
In order to realize the maximum protection against ESD pulses with the PAC DN006, care must be taken in the PCB layout
to minimize the parasitic series inductance to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of
a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the
power supply is represented by L
1
. The voltage V
Z
on the line being protected is:
V
Z
= Forward voltage drop of D
1
+ L
1
x d(I
esd
)/dt + V
Supply
where I
esd
is the ESD current pulse, and V
Supply
is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, consider the case of an ESD
pulse that rises from zero to 10 Amps in 1nS. Here d(I
esd
)/dt can be approximated by
∆I
esd
/∆t, or 10/(1x10
-9
). So each
nano Henry of series inductance (L
1
) will lead to a 10V increment in V
Z
.
©1999 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
Rev 1 3/99
CALIFORNIA MICRO DEVICES
PAC DN006
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to increased
negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit
a much higher output impedance to fast transient current spikes. In the V
Z
equation above, the V
Supply
term, in reality, is
given by (V
DC
+ I
esd
x R
out
), where V
DC
and R
out
are the nominal supply DC output voltage and effective output impedance
of the power supply respectively. As an example, a R
out
of 1 ohm would result in a 10V increment in V
Z
for a peak I
esd
of
10A. To mitigate this effect, a high frequency bypass capacitor should be connected between the V
P
pin of the PAC DN006
and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred
by the ESD pulse with minimal change in Vp. Typically a value in the 0.1 µF to 0.2 µF range is adequate for IEC-1000-4-2,
level 4 contact discharge protection (8KV). Ceramic chip capacitors mounted with short printed circuit board traces are a
good choice for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics.
For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series
inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the
maximum supply voltage.
As a general rule, the PAC DN006 should be located as close as possible to the point of entry of expected electrostatic
discharges. The power supply bypass capacitor mentioned above should be as close to the PAC DN006 as possible, with
minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Implementation Examples
ESD events are very high speed pulses with rise times in the range of 1 nS or less. To effectively use the PAC DN006, the
following design guidelines must be observed (as discussed in the application section):
1. The inductance from the V
N
and V
P
connections of the PAC DN006 to ground must be very low. This includes the path
through the V
P
decoupling capacitor to ground and the path to the power supply (as discussed above).
2. The inductance between the connector pin to be protected and the PAC DN006 channel input pin must be kept to a
minimum. (If there is a large inductance here, the ESD event will find a lower impedance path which will more likely be
through the device to be protected.) Figure 2 shows the implementation schematic and Figure 3 shows a possible layout
for the PAC DN006. In Figure 3, notice the large V
CC
and ground areas with multiple via connections to the underlying
reference planes and the positioning of the bypass capacitor. Note how the signal lines to be protected flow from the
connector to the PAC DN006 and then out to the device to be protected (Figures 3, 4, and 5). This daisy chaining
provides a low impedance path from the connector to the PAC DN006 and a higher impedance path from the PAC DN006
to the protected device.
POSITIVE SUPPLY RAIL
D
1
CHANNEL
INPUT
DECOUPLING
CAPACITOR
0.1uF
LINE BEING
PROTECTED
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
D
2
ONE
CHANNEL
OF
PAC DN006
POWER
SUPPLY
OPTIONAL
ZENER DIODE
FOR EXTRA
PROTECTION
GROUND RAIL
Figure 2
© 1999 Calirornia Micro Devices Corp. All rights reserved.
3/99 Rev 1
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
CALIFORNIA MICRO DEVICES
PAC DN006
Figure 4
Figure 3
Figure 5
© 1999 Calirornia Micro Devices Corp. All rights reserved.
3/99 Rev 1
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4
CALIFORNIA MICRO DEVICES
MSOP - TOP VIEW
PAC DN006
Power Derating Curve
CMD
Mechanical Specifications
Lead Plating
Tin-Lead
Lead Material
Copper Alloy
Lead Coplanarity
0.004" (0.102mm)
Substrate Material
Silicon
Body Material
Molded Epoxy
Flammability
UL94V-0
Package Dimensions, Power Dissipation & Information
Package
MSOP
Pins #
8
JEDEC
MO 187
mm
inches
min
max
min
max
0.94
1.09
0.037
0.043
A
0.05
0.15
0.002
0.006
A
1
0.20
0.40
0.008
0.016
B
0.08
0.23
0.003
0.009
C
2.90
3.10
0.114
0.122
D
2.90
3.10
0.114
0.122
E
0.64 BSC
0.025 BSC
e
4.78
4.98
0.188
0.196
H
0.40
0.69
0.016
0.027
L
200mW
P
D
@ 70 C
# / tube
50 pcs
# / tape & reel
2,500 pcs
©1999 California Micro Devices Corp. All rights reserved.
5
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
Rev 1 3/99
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