TSS923(E)/933(E)
HSDLink Transmitter/Receiver
1. Introduction
The TSS923 Transmitter and TSS933 Receiver are point
to point communications building blocks that transfer
data over high speed serial links at 160 up to 400
Mbauds/s (depending on the data encoder/decoder
selection).
Eight bits of user data or protocol information are loaded
into the Transmitter and are encoded within the 8B10B or
8B16B mode and then serialized. Serial data is shifted out
of the three differential positive ECL (PECL) serial ports
at the bit rate. The bit rate is 10 times or 16 times the byte
rate (depends on the encoded mode). The Receiver
accepts the serial bit stream at its differential line inputs
and, using an on chip PLL, recovers the serial bit rate
information for a correct data retiming. The bit stream is
deserialized, decoded within the 8B10B or 8B16B mode
and checked for transmission errors. Recovered bytes are
presented in parallel to the receiving host along with a
byte rate clock. The 8B/10B or 8B/16B encoder/decoder
can be disabled in systems that already encode or
scramble the transmitted data. HSDLink chipset are ideal
for a variety of applications where a parallel interface can
be replaced with a high speed point to point serial link.
Applications include,
D
D
D
D
Interconnecting workstations
Servers
Mass storage
Video transmission equipment.
2. Features
D
D
D
D
D
D
D
D
D
D
D
Fibre Channel compliant
IBM ESCON
1
compliant
ATM compliant
HOTLink
2
package and pinout compatible
Case Temperature range: -55 ºC up to 125 ºC
190 up to 400 Mbaud/s link data rate
TTL synchronous I/O
8B/10B encoded mode
3
8B/16B Hamming encoded mode
160 up to 400 Mbaud/s link data rate (8B/16B)
160 up to 330 Mbaud/s link data rate (8B/10B)
D
D
D
D
D
D
D
D
D
D
Hardened design for SEU tolerance (8B/16B)
Bypass mode
Built In Self Test
Dose Rate > 30 krad
Triple PECL 100K serial outputs
Dual PECL 100K serial inputs
On-chip Phase Locked Loop
Single +5V power supply
28-pin MQFPJ/LCC
(*)
/SOIC
(*)
/PLCC
(*)
0.8
µ
m BiCMOS (Radiation Tolerant for “E”
versions)
1. ESCON is a registered trademark of IBM
2. HOTLink is a trademark of Cypress Semiconductor Corporation
3. US Patent 4,488,739 “8B/10B Partitioned Block Transmission Code” Dec 4,1984
(*) Preview
MATRA MHS
Rev. E (27 Mar.97)
1
Preliminary Information
TSS923(E)/933(E)
Table 1: Frequency and Data rate ranges
8B/10B Mode
Data Rate (Mbit/s)
Byte rate Clock (MHz)
Serial Link Data rate (Mbaud/s)
128 up to 264
16 up to 33
160 up to 330
8B/16B Mode
80 up to 200
10 up to 25
160 up to 400
Table 2: TSS923 Transmitter Temperature Range & Associated Packages
Operating Range
Commercial
Industriel
Military
Temperature
Ambient Temperature Range = 0 ºC up to 70 ºC
Ambient Temperature Range = -40 º C up to 85 ºC
Case Temperature range = -55 ºC up to 125 ºC
Package
SOIC28
(*)
/PLCC28
(*)
PLCC28
(*)
MQFPJ28/LCC28
(*)
Table 3: TSS933 Receiver Temperature Range & Associated Packages
Operating Range
Commercial
Industriel
Military
Temperature
Ambient Temperature Range = 0 ºC up to 70 ºC
Ambient Temperature Range = -40 ºC up to 85 ºC
Case Temperature range = -55 ºC up to 125 ºC
Package
SOIC28
(*)
/PLCC28
(*)
PLCC 28
(*)
MQFPJ28/LCC28
(*)
3. Transmitter Pin Description
Table 4: TSS923 Transmitter
Name
I/O
Description (valid for 8B10B or 8B16B encoding)
Parallel Data Input
ENA=0, data are clocked into the input register on the rising edge of CKW.
ENA=1 and ENN=0, data are clocked into the input register on the next rising edge of CKW.
ENA=ENN=1, a SYNC character is sent.
When the BYPASS mode is choosen, D
0..7
become D
b,c,d,e,i,f,g,h
.
Special Character / Data Select
SC/D=1, when CKW rises causes the transmitter to encode the pattern on D
0..7
as a protocol or control
code (Special Character).
SC/D=0, when CKW rises causes the transmitter to encode the pattern on D
0..7
as a data pattern (8B/10B
or 8B/16B).
When the BYPASS mode is selected, SC/D becomes D
a
.
Send Violation Symbol
SVS=1, when CKW rises, a Violation symbol is encoded and sent while the data on the parallel inputs is
ignored.
SVS=0, D
0..7
and SC/D are encoded.
SVS pin overrides the GPA BIST, and forces the transmission of a Violation code and reset the sequence.
When the BYPASS mode is selected, SVS becomes D
j
.
D
0..7
(D
b..h
)
TTL In
SC/D
(Da)
TTL In
SVS
(Dj)
TTL In
MATRA MHS
Rev. E (27 Mar.97)
5
Preliminary Information
FPGA/CPLD
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