Advance Data Sheet
September 2001
CelXpres
™
T8207
ATM Interconnect
1
1.1
s
s
Product Overview
Features
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Programmable priority for control/data cells trans-
mission onto cell bus
Eight GPIO pins
JTAG support
Optional monitoring of misrouted cells
Microprocessor interface, supporting both
Motor-
ola
®
and
Intel
®
modes (multiplexed and nonmulti-
plexed)
Control cell transmission and reception through
microprocessor port
Single 3.3 V power supply
3.3 V TTL I/O (5 V tolerant)
272-pin PBGA package
Industrial temperature range (–40 °C to +85 °C)
Hot insertion capability
Compatible with
Transwitch CellBus
®
s
s
s
s
> OC-3 transport capability
UTOPIA level 1 and 2 (8-bit) cell-level handshake
interface (ATM or PHY layers)
32 multi-PHY (MPHY) operation
Shared UTOPIA mode
Egress SDRAM buffer support to expand UTOPIA
output priority queues for 32K to 512K cells:
— 64 queues configurable up to four queues per
PHY with programmable sizes
— Programmable number of UTOPIA output
queues with four levels of priority
Support of ATM traffic management via partial
packet discard (PPD), forward explicit congestion
notification (FECN), and the cell loss priority (CLP)
bit
Programmable slew rate GTL+ I/O:
— 1.7 Gbits/s cell bus operation
— Programmable as bus arbiter
Flexible per port cell counters
Cell header translation and insertion with virtual
path identifier (VPI) and virtual channel identifier
(VCI) via external SRAM (up to 64K entries)
Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow control (GFC) insertion
Programmable operations and maintenance and
resource management (OAM/RM) cell routing
Support of multicast and broadcast cells per PHY
s
s
s
s
s
s
s
s
s
s
s
s
1.2
s
Applications
s
s
Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexer (DSLAMs)
Access gateways
Access multiplexers/concentrators
Multiservice access equipment platforms
s
s
s
s
s
s
CelXpres
T8207
ATM Interconnect
Advance Data Sheet
September 2001
Table of Contents
Contents
1
Page
Product Overview................................................................................................................................................1
1.1 Features ....................................................................................................................................................1
1.2 Applications ...............................................................................................................................................1
1.3 Description ................................................................................................................................................8
1.4 Conventions ............................................................................................................................................11
1.5 Glossary ..................................................................................................................................................12
2 Pin Description ..................................................................................................................................................13
3 Powerup/Reset Sequence ................................................................................................................................20
4 Hot Insertion......................................................................................................................................................21
5 PLL Configuration .............................................................................................................................................22
6 Microprocessor Interface ..................................................................................................................................23
6.1 Microprocessor Interface Configuration ..................................................................................................23
6.2 Microprocessor Interrupts........................................................................................................................23
6.3 Accessing the
CelXpres
T8207 via Microprocessor Interface.................................................................23
6.3.1 Accessing the Extended Memory Registers...............................................................................24
6.3.1.1 Extended Memory Writes.............................................................................................24
6.3.1.2 Extended Memory Reads.............................................................................................24
6.3.2
CelXpres
T8207 Access Performance .......................................................................................25
7 General-Purpose I/O (GPIO) ............................................................................................................................26
8 Look-Up Table ..................................................................................................................................................27
8.1 Look-Up Table RAM................................................................................................................................27
8.2 Organization ............................................................................................................................................28
8.3 Look-Up Procedure .................................................................................................................................33
8.4 Extended Records...................................................................................................................................36
8.5 Diagnostics..............................................................................................................................................41
8.6 Setup .......................................................................................................................................................41
9 UTOPIA Interface..............................................................................................................................................42
9.1 Incoming UTOPIA Cell Interface .............................................................................................................43
9.1.1 Incoming PHY Mode (Cells Received by T8207) .......................................................................43
9.1.2 Incoming ATM Mode (Cells Received by T8207).......................................................................43
9.2 Outgoing UTOPIA Cell Interface .............................................................................................................44
9.2.1 Outgoing PHY Mode (Cells Sent by T8207)...............................................................................44
9.2.2 Outgoing ATM Mode (Cells Sent by T8207) ..............................................................................45
9.3 Counters..................................................................................................................................................46
9.4 55-Byte UTOPIA Mode............................................................................................................................47
9.5 Shared UTOPIA Mode ............................................................................................................................48
9.6 UTOPIA Pin Modes .................................................................................................................................50
9.7 UTOPIA Clocking ....................................................................................................................................53
10 Cell Bus Interface..............................................................................................................................................54
10.1 General Architecture ...............................................................................................................................54
10.2 Cell Bus Frames......................................................................................................................................56
10.3 Cell Bus Routing Headers .......................................................................................................................59
10.3.1 Control Cells...............................................................................................................................59
10.3.2 Data Cells...................................................................................................................................60
10.3.3 Loopback Cells...........................................................................................................................60
10.3.4 Multicast Routing........................................................................................................................60
10.3.5 Broadcast Routing......................................................................................................................61
10.4 Cell Bus Arbitration..................................................................................................................................61
10.5 Cell Bus Monitoring .................................................................................................................................62
10.6 GTL+ Logic..............................................................................................................................................62
10.7 Cell Bus Write and Read Clocks .............................................................................................................63
2
Agere Systems Inc.
Advance Data Sheet
September 2001
CelXpres
T8207
ATM Interconnect
Table of Contents
(continued)
Contents
Page
11 SDRAM Interface.............................................................................................................................................. 64
11.1 Memory Configuration............................................................................................................................. 64
11.2 Powerup Sequence................................................................................................................................. 64
11.3 SDRAM Interface Timing ........................................................................................................................ 65
11.4 Queuing .................................................................................................................................................. 66
11.5 SDRAM Refresh ..................................................................................................................................... 72
11.6 SDRAM Throughput................................................................................................................................ 73
12 Traffic Management.......................................................................................................................................... 74
12.1 Cell Loss Priority (CLP)........................................................................................................................... 74
12.2 Forward Explicit Congestion Notification (FECN) ................................................................................... 74
12.3 Partial Packet Discard (PPD) .................................................................................................................. 74
13 JTAG Test Access Port .................................................................................................................................... 75
13.1 Instruction Register ................................................................................................................................. 75
13.2 Boundary-Scan Register ......................................................................................................................... 76
14 Registers........................................................................................................................................................... 79
14.1 Register Types........................................................................................................................................ 79
14.2 Direct Memory Access Registers ............................................................................................................ 82
14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access
Registers 30h—37h ................................................................................................................... 86
14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access
Registers 30h—37h ................................................................................................................... 88
14.2.3 General-Purpose I/O Control Registers ..................................................................................... 90
14.2.4 Control Cells .............................................................................................................................. 91
14.2.5 Multicast Memories .................................................................................................................... 92
14.3 Extended Memory Registers................................................................................................................... 93
14.3.1 Main Registers ........................................................................................................................... 93
14.3.2 UTOPIA Registers ................................................................................................................... 106
14.3.2.1 TX UTOPIA Configuration ......................................................................................... 108
14.3.2.2 TX UTOPIA Monitoring .............................................................................................. 125
14.3.2.3 RX UTOPIA Monitoring.............................................................................................. 126
14.3.3 SDRAM Registers .................................................................................................................... 128
14.3.3.1 SDRAM Control Memory ........................................................................................... 135
14.3.4 Various Internal Memories ....................................................................................................... 137
14.3.4.1 Control Cell Memories ............................................................................................... 137
14.3.4.2 Multicast Number Memories ...................................................................................... 138
14.3.4.3 PPD State Memory ....................................................................................................140
14.3.5 External Memories ................................................................................................................... 141
14.3.5.1 Look-Up Translation Memory .................................................................................... 141
14.3.5.2 SDRAM Buffer Memory .............................................................................................141
15 Absolute Maximum Ratings ............................................................................................................................ 142
16 Recommended Operating Conditions............................................................................................................. 142
17 Handling Precautions...................................................................................................................................... 142
18 Electrical Requirements and Characteristics .................................................................................................. 143
18.1 Crystal Information................................................................................................................................ 143
18.2 dc Electrical Characteristics .................................................................................................................. 144
19 Timing Requirements...................................................................................................................................... 145
19.1 Microprocessor Interface Timing........................................................................................................... 146
19.2 UTOPIA Timing..................................................................................................................................... 152
19.3 External LUT Memory Timing ............................................................................................................... 153
19.4 Cell Bus Timing..................................................................................................................................... 155
19.5 SDRAM Interface Timing ...................................................................................................................... 156
20 Outline Diagram.............................................................................................................................................. 157
21 Ordering Information....................................................................................................................................... 158
Agere Systems Inc.
3
CelXpres
T8207
ATM Interconnect
Advance Data Sheet
September 2001
Table of Contents
(continued)
Figure
Page
Figure 1. Functional Block Diagram ......................................................................................................................... 9
Figure 2. Dual Bus Implementation ........................................................................................................................ 10
Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 19
Figure 4. Translation RAM Memory Map—8-Byte Records, for Up to 16 Ports ..................................................... 29
Figure 5. Translation RAM Memory Map—8-Byte Records, for Greater than 16 Ports...........................................30
Figure 6. Translation Record Types—8-Byte Records........................................................................................... 31
Figure 7. Translation RAM Flow Diagram .............................................................................................................. 35
Figure 8. Translation Record Types—Extended Mode .......................................................................................... 37
Figure 9. Translation RAM Memory Map—Extended Mode, for Up to 16 Ports..................................................... 38
Figure 10. Translation RAM Memory Map—Extended Mode, for Greater than 16 Ports ........................................39
Figure 11. Queue Priority Multiplexing ................................................................................................................... 46
Figure 12. TX UTOPIA Cell Handling ..................................................................................................................... 47
Figure 13. TX UTOPIA Bus Sharing....................................................................................................................... 49
Figure 14. Cell Bus Frame Format (Bit Positions for 16 User Mode) ..................................................................... 56
Figure 15. Cell Bus Frame Format (Bit Positions for 32 User Mode) ..................................................................... 57
Figure 16. Cell Bus Routing Headers ..................................................................................................................... 59
Figure 17. GTL+ External Circuitry ......................................................................................................................... 62
Figure 18. SDRAM Timing Parameters .................................................................................................................. 65
Figure 19. Crystal ................................................................................................................................................. 143
Figure 20. Negative Resistance Plot .................................................................................................................... 143
Figure 21. Nonmultiplexed
Intel
Mode Write Access Timing ................................................................................ 146
Figure 22. Nonmultiplexed
Intel
Mode Read Access Timing................................................................................ 146
Figure 23.
Motorola
Mode Write Access Timing................................................................................................... 148
Figure 24.
Motorola
Mode Read Access Timing .................................................................................................. 148
Figure 25. Multiplexed
Intel
Mode Write Access Timing....................................................................................... 150
Figure 26. Multiplexed
Intel
Mode Read Access Timing ...................................................................................... 150
Figure 27. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 28. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 29. Cell Bus Timing ................................................................................................................................... 155
Figure 30. SDRAM Interface Timing..................................................................................................................... 156
4
Agere Systems Inc.
Advance Data Sheet
September 2001
CelXpres
T8207
ATM Interconnect
Table of Contents
(continued)
Table
Page
Table 1. UTOPIA Pins ........................................................................................................................................... 13
Table 2. Cell Bus Pins ........................................................................................................................................... 14
Table 3. SDRAM Interface Pins ............................................................................................................................ 15
Table 4. Microprocessor Interface Pins ................................................................................................................. 16
Table 5. Translation SRAM Interface ..................................................................................................................... 17
Table 6. JTAG Pins ............................................................................................................................................... 17
Table 7. General-Purpose Pins ............................................................................................................................. 18
Table 8. Power Pins .............................................................................................................................................. 18
Table 9. Loop Filter Register Settings .................................................................................................................... 22
Table 10. Access Times ........................................................................................................................................ 25
Table 11. Active and Ignore Truth Table ............................................................................................................... 31
Table 12. VPI Value Truth Table ........................................................................................................................... 32
Table 13. OAM Routing Control Truth Table ......................................................................................................... 32
Table 14. F5 Translation Record Addresses Table—8-Byte Records ................................................................... 33
Table 15. F5 Translation Record Addresses Table—Extended Mode ................................................................... 40
Table 16. Port Numbering for MPHY Configurations ............................................................................................ 51
Table 17. Supported Memory Configurations ....................................................................................................... 64
Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 ................. 67
Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports ................................................ 69
Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0................... 71
Table 21. Instruction Register ............................................................................................................................... 75
Table 22. Boundary-Scan Register Descriptions .................................................................................................. 76
Table 23. Register Map ........................................................................................................................................... 79
Table 24. Identification 0 (IDNT0) (00h) ................................................................................................................ 82
Table 25. Identification 1 (IDNT1) (01h) ................................................................................................................. 82
Table 26. Identification 2 (IDNT2) (02h) ................................................................................................................ 82
Table 27. Direct Configuration/Control Register (DCCR) (28h) ............................................................................. 83
Table 28. Interrupt Service Request (ISREQ) (29h) ............................................................................................. 84
Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah) ......................................................................................... 84
Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ......................................................................................... 85
Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) ................................................................................ 85
Table 32. GTL+ Control (GTLCNTRL) (2Fh)........................................................................................................... 85
Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h)............................................................. 86
Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h)............................................................. 86
Table 35. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h)............................................................. 86
Table 36. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h)............................................................. 86
Table 37. Extended Memory Access (Little Endian) (EMA_LE) (34h) ................................................................... 86
Table 38. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) ............................................................. 87
Table 39. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ............................................................ 87
Table 40. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h)............................................................... 88
Table 41. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h)............................................................... 88
Table 42. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h)............................................................... 88
Table 43. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)............................................................... 88
Table 44. Extended Memory Access (Big Endian) (EMA_BE) (34h) ..................................................................... 89
Table 45. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) .............................................................. 89
Table 46. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) ............................................................... 89
Table 47. GPIO Output Enable (GPIO_OE) (39h) ................................................................................................. 90
Table 48. GPIO Output Value (GPIO_OV) (3Bh) ................................................................................................... 90
Agere Systems Inc.
5
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